Skip to content

Commit 0e3cc29

Browse files
sfe-SparkFrodpgeorge
sfe-SparkFro
authored and
dpgeorge
committed
mimxrt: Add PSRAM implementation.
This commit adds PSRAM support for Teensy 4.1 and other mimxrt boards. It's enabled by default for Teensy 4.1. This implementation is based on the Teensy Arduino core PSRAM code, and Paul Stoffregen has agreed for it to be published here under the MIT license, see micropython#18288 (comment) This addresses issue micropython#18281. Signed-off-by: Dryw Wade <dryw.wade@sparkfun.com>
1 parent 96bce47 commit 0e3cc29

6 files changed

Lines changed: 331 additions & 1 deletion

File tree

‎ports/mimxrt/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -266,6 +266,7 @@ SRC_C += \
266266
network_lan.c \
267267
pendsv.c \
268268
pin.c \
269+
psram.c \
269270
sdcard.c \
270271
sdio.c \
271272
systick.c \

‎ports/mimxrt/boards/TEENSY41/mpconfigboard.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -136,3 +136,6 @@
136136
{ IOMUXC_GPIO_B1_11_ENET_RX_ER, 0, 0xB0E9u }, \
137137
{ IOMUXC_GPIO_B1_15_ENET_MDIO, 0, 0xB0E9u }, \
138138
{ IOMUXC_GPIO_B1_14_ENET_MDC, 0, 0xB0E9u },
139+
140+
// Enable PSRAM support
141+
#define MICROPY_HW_ENABLE_PSRAM (1)

‎ports/mimxrt/main.c‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,7 @@
3737
#include "ticks.h"
3838
#include "led.h"
3939
#include "pendsv.h"
40+
#include "psram.h"
4041
#include "modmachine.h"
4142
#include "modmimxrt.h"
4243

@@ -67,6 +68,10 @@ int main(void) {
6768
ticks_init();
6869
pendsv_init();
6970

71+
#if MICROPY_HW_ENABLE_PSRAM
72+
size_t psram_size = configure_external_ram();
73+
#endif
74+
7075
#if MICROPY_PY_LWIP
7176
// lwIP doesn't allow to reinitialise itself by subsequent calls to this function
7277
// because the system timeout list (next_timeout) is only ever reset by BSS clearing.
@@ -101,7 +106,20 @@ int main(void) {
101106

102107
mp_cstack_init_with_top(&_estack, &_estack - &_sstack);
103108

109+
#if MICROPY_HW_ENABLE_PSRAM
110+
if (psram_size) {
111+
#if MICROPY_GC_SPLIT_HEAP
112+
gc_init(&_gc_heap_start, &_gc_heap_end);
113+
gc_add((void *)PSRAM_BASE, (void *)(PSRAM_BASE + psram_size));
114+
#else
115+
gc_init((void *)PSRAM_BASE, (void *)(PSRAM_BASE + psram_size));
116+
#endif
117+
} else {
118+
gc_init(&_gc_heap_start, &_gc_heap_end);
119+
}
120+
#else
104121
gc_init(&_gc_heap_start, &_gc_heap_end);
122+
#endif
105123
mp_init();
106124

107125
#if MICROPY_PY_NETWORK

‎ports/mimxrt/mpconfigport.h‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,13 +35,20 @@ uint32_t trng_random_u32(void);
3535
// Config level
3636
#define MICROPY_CONFIG_ROM_LEVEL (MICROPY_CONFIG_ROM_LEVEL_FULL_FEATURES)
3737

38+
#ifndef MICROPY_HW_ENABLE_PSRAM
39+
#define MICROPY_HW_ENABLE_PSRAM (0)
40+
#endif
41+
3842
// Memory allocation policies
39-
#if MICROPY_HW_SDRAM_AVAIL
43+
#if MICROPY_HW_SDRAM_AVAIL || MICROPY_HW_ENABLE_PSRAM
4044
#define MICROPY_GC_STACK_ENTRY_TYPE uint32_t
4145
#else
4246
#define MICROPY_GC_STACK_ENTRY_TYPE uint16_t
4347
#endif
4448
#define MICROPY_ALLOC_PATH_MAX (256)
49+
#ifndef MICROPY_GC_SPLIT_HEAP
50+
#define MICROPY_GC_SPLIT_HEAP MICROPY_HW_ENABLE_PSRAM
51+
#endif
4552

4653
// MicroPython emitters
4754
#define MICROPY_PERSISTENT_CODE_LOAD (1)

‎ports/mimxrt/psram.c‎

Lines changed: 265 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,265 @@
1+
/*
2+
* This file is part of the MicroPython project, http://micropython.org/
3+
*
4+
* The MIT License (MIT)
5+
*
6+
* Copyright (c) 2019 Paul Stoffregen
7+
* 2026 Dryw Wade
8+
*
9+
* Permission is hereby granted, free of charge, to any person obtaining a copy
10+
* of this software and associated documentation files (the "Software"), to deal
11+
* in the Software without restriction, including without limitation the rights
12+
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13+
* copies of the Software, and to permit persons to whom the Software is
14+
* furnished to do so, subject to the following conditions:
15+
*
16+
* The above copyright notice and this permission notice shall be included in
17+
* all copies or substantial portions of the Software.
18+
*
19+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
22+
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24+
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25+
* THE SOFTWARE.
26+
*/
27+
28+
// This implementation is adapted from here:
29+
// https://github.com/PaulStoffregen/cores/blob/10025393e83ca9f4dc5646643a41cb2f32022ae4/teensy4/startup.c#L421-L615
30+
#include "py/mphal.h"
31+
#include "fsl_flexspi.h"
32+
33+
#if MICROPY_HW_ENABLE_PSRAM
34+
35+
/*!
36+
* @brief Clock divider value.
37+
*
38+
* See https://www.pjrc.com/teensy/IMXRT1060RM_rev3_annotations.pdf (p1010 and p1050)
39+
*/
40+
typedef enum _clock_mux_value {
41+
kCLOCK_Flexspi2Mux_396MHz = 0U, /*!< FLEXSPI2 clock source is PLL2 PFD2. */
42+
kCLOCK_Flexspi2Mux_720MHz = 1U, /*!< FLEXSPI2 clock source is PLL3 PFD0. */
43+
kCLOCK_Flexspi2Mux_664_62MHz = 2U, /*!< FLEXSPI2 clock source is PLL3 PFD1. */
44+
kCLOCK_Flexspi2Mux_528MHz = 3U, /*!< FLEXSPI2 clock source is PLL2 (pll2_main_clk). */
45+
} clock_mux_value_t;
46+
47+
static void flexspi2_command(uint32_t index, uint32_t addr, flexspi_port_t port) {
48+
flexspi_transfer_t xfer = {
49+
.deviceAddress = addr,
50+
.port = port,
51+
.cmdType = kFLEXSPI_Command,
52+
.seqIndex = index,
53+
.SeqNumber = 1,
54+
.data = NULL,
55+
.dataSize = 0,
56+
};
57+
FLEXSPI_TransferBlocking(FLEXSPI2, &xfer);
58+
FLEXSPI_ClearInterruptStatusFlags(FLEXSPI2, kFLEXSPI_IpCommandExecutionDoneFlag);
59+
}
60+
61+
static uint32_t flexspi2_psram_id(uint32_t addr, flexspi_port_t port) {
62+
uint32_t id = 0;
63+
flexspi_transfer_t xfer = {
64+
.deviceAddress = addr,
65+
.port = port,
66+
.cmdType = kFLEXSPI_Read,
67+
.seqIndex = 3,
68+
.SeqNumber = 1,
69+
.data = &id,
70+
.dataSize = 4,
71+
};
72+
FLEXSPI_TransferBlocking(FLEXSPI2, &xfer);
73+
FLEXSPI_ClearInterruptStatusFlags(FLEXSPI2,
74+
kFLEXSPI_IpCommandExecutionDoneFlag | kFLEXSPI_IpRxFifoWatermarkAvailableFlag);
75+
return id;
76+
}
77+
78+
/**
79+
* \return size of PSRAM in MBytes, or 0 if not present
80+
*/
81+
static uint8_t flexspi2_psram_size(uint32_t addr, flexspi_port_t port) {
82+
uint8_t result = 0; // assume we don't have PSRAM at this address
83+
flexspi2_command(0, addr, port); // exit quad mode
84+
flexspi2_command(1, addr, port); // reset enable
85+
flexspi2_command(2, addr, port); // reset (is this really necessary?)
86+
uint32_t id = flexspi2_psram_id(addr, port);
87+
88+
switch (id & 0xFFFF)
89+
{
90+
default:
91+
break;
92+
93+
case 0x5D0D: // AP / Ipus / ESP / Lyontek
94+
result = 8;
95+
break;
96+
97+
case 0x5D9D: // ISSI
98+
switch ((id >> 21) & 0x7) // get size (Datasheet Table 6.2)
99+
{
100+
case 0b011:
101+
result = 8;
102+
break;
103+
case 0b100:
104+
result = 16;
105+
break;
106+
}
107+
break;
108+
}
109+
110+
return result;
111+
}
112+
113+
size_t configure_external_ram() {
114+
// initialize pins
115+
IOMUXC->SW_PAD_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22] = 0x1B0F9; // 100K pullup, strong drive, max speed, hyst
116+
IOMUXC->SW_PAD_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23] = 0x110F9; // keeper, strong drive, max speed, hyst
117+
IOMUXC->SW_PAD_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24] = 0x1B0F9; // 100K pullup, strong drive, max speed, hyst
118+
IOMUXC->SW_PAD_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25] = 0x100F9; // strong drive, max speed, hyst
119+
IOMUXC->SW_PAD_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26] = 0x170F9; // 47K pullup, strong drive, max speed, hyst
120+
IOMUXC->SW_PAD_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27] = 0x170F9; // 47K pullup, strong drive, max speed, hyst
121+
IOMUXC->SW_PAD_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28] = 0x170F9; // 47K pullup, strong drive, max speed, hyst
122+
IOMUXC->SW_PAD_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29] = 0x170F9; // 47K pullup, strong drive, max speed, hyst
123+
124+
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22] = 8 | 0x10; // ALT1 = FLEXSPI2_A_SS1_B (Flash)
125+
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23] = 8 | 0x10; // ALT1 = FLEXSPI2_A_DQS
126+
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24] = 8 | 0x10; // ALT1 = FLEXSPI2_A_SS0_B (RAM)
127+
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25] = 8 | 0x10; // ALT1 = FLEXSPI2_A_SCLK
128+
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26] = 8 | 0x10; // ALT1 = FLEXSPI2_A_DATA0
129+
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27] = 8 | 0x10; // ALT1 = FLEXSPI2_A_DATA1
130+
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28] = 8 | 0x10; // ALT1 = FLEXSPI2_A_DATA2
131+
IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29] = 8 | 0x10; // ALT1 = FLEXSPI2_A_DATA3
132+
133+
IOMUXC->SELECT_INPUT_1[kIOMUXC_FLEXSPI2_IPP_IND_DQS_FA_SELECT_INPUT] = 1; // GPIO_EMC_23 for Mode: ALT8, pg 986
134+
IOMUXC->SELECT_INPUT_1[kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT0_SELECT_INPUT] = 1; // GPIO_EMC_26 for Mode: ALT8
135+
IOMUXC->SELECT_INPUT_1[kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT1_SELECT_INPUT] = 1; // GPIO_EMC_27 for Mode: ALT8
136+
IOMUXC->SELECT_INPUT_1[kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT2_SELECT_INPUT] = 1; // GPIO_EMC_28 for Mode: ALT8
137+
IOMUXC->SELECT_INPUT_1[kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT3_SELECT_INPUT] = 1; // GPIO_EMC_29 for Mode: ALT8
138+
IOMUXC->SELECT_INPUT_1[kIOMUXC_FLEXSPI2_IPP_IND_SCK_FA_SELECT_INPUT] = 1; // GPIO_EMC_25 for Mode: ALT8
139+
140+
// turn on clock (QSPI flash & PSRAM chips usually spec max clock 100 to 133 MHz)
141+
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, kCLOCK_Flexspi2DivBy6); // 88.0 MHz
142+
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, kCLOCK_Flexspi2Mux_528MHz); // 88.0 MHz
143+
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, kCLOCK_Flexspi2DivBy4); // 99.0 MHz
144+
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, kCLOCK_Flexspi2Mux_396MHz); // 99.0 MHz
145+
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, kCLOCK_Flexspi2DivBy7); // 102.9 MHz
146+
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, kCLOCK_Flexspi2Mux_720MHz); // 102.9 MHz
147+
CLOCK_SetDiv(kCLOCK_Flexspi2Div, kCLOCK_Flexspi2DivBy5); // 105.6 MHz
148+
CLOCK_SetMux(kCLOCK_Flexspi2Mux, kCLOCK_Flexspi2Mux_528MHz); // 105.6 MHz
149+
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, kCLOCK_Flexspi2DivBy6); // 110.8 MHz
150+
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, kCLOCK_Flexspi2Mux_664_62MHz); // 110.8 MHz
151+
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, kCLOCK_Flexspi2DivBy6); // 120.0 MHz
152+
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, kCLOCK_Flexspi2Mux_720MHz); // 120.0 MHz
153+
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, kCLOCK_Flexspi2DivBy4); // 132.0 MHz
154+
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, kCLOCK_Flexspi2Mux_528MHz); // 132.0 MHz
155+
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, kCLOCK_Flexspi2DivBy5); // 144.0 MHz
156+
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, kCLOCK_Flexspi2Mux_720MHz); // 144.0 MHz
157+
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, kCLOCK_Flexspi2DivBy4); // 166.2 MHz
158+
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, kCLOCK_Flexspi2Mux_664_62MHz); // 166.2 MHz
159+
// CLOCK_SetDiv(kCLOCK_Flexspi2Div, kCLOCK_Flexspi2DivBy3); // 176.0 MHz
160+
// CLOCK_SetMux(kCLOCK_Flexspi2Mux, kCLOCK_Flexspi2Mux_528MHz); // 176.0 MHz
161+
162+
flexspi_config_t flexspi_config = {
163+
.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackFromDqsPad,
164+
.enableSckFreeRunning = false,
165+
.enableCombination = false,
166+
.enableDoze = false,
167+
.enableHalfSpeedAccess = false,
168+
.enableSckBDiffOpt = false,
169+
.enableSameConfigForAll = false,
170+
.seqTimeoutCycle = 0xFFFF,
171+
.ipGrantTimeoutCycle = 0xFF,
172+
.txWatermark = 0,
173+
.rxWatermark = 0,
174+
.ahbConfig = {
175+
.enableAHBWriteIpTxFifo = false,
176+
.enableAHBWriteIpRxFifo = false,
177+
.ahbGrantTimeoutCycle = 0xFF,
178+
.ahbBusTimeoutCycle = 0xFFFF,
179+
.resumeWaitCycle = 0x20,
180+
.buffer = {
181+
{.priority = 0, .masterIndex = 0, .bufferSize = 512, .enablePrefetch = true},
182+
{.priority = 0, .masterIndex = 0, .bufferSize = 512, .enablePrefetch = true},
183+
{.priority = 0, .masterIndex = 0, .bufferSize = 0, .enablePrefetch = false},
184+
{.priority = 0, .masterIndex = 0, .bufferSize = 0, .enablePrefetch = false},
185+
},
186+
.enableClearAHBBufferOpt = false,
187+
.enableReadAddressOpt = false,
188+
.enableAHBPrefetch = false,
189+
.enableAHBBufferable = false,
190+
.enableAHBCachable = false,
191+
},
192+
};
193+
FLEXSPI_Init(FLEXSPI2, &flexspi_config);
194+
195+
FLEXSPI_DisableInterrupts(FLEXSPI2, kFLEXSPI_AllInterruptFlags);
196+
197+
flexspi_device_config_t flexspi_device_config = {
198+
.flexspiRootClk = 0,
199+
.isSck2Enabled = false,
200+
.flashSize = 1 << 16, // Default value, will be updated later
201+
.CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
202+
.CSInterval = 0,
203+
.CSHoldTime = 1,
204+
.CSSetupTime = 1,
205+
.dataValidTime = 0,
206+
.columnspace = 0,
207+
.enableWordAddress = false,
208+
.AWRSeqIndex = 6,
209+
.AWRSeqNumber = 1,
210+
.ARDSeqIndex = 5,
211+
.ARDSeqNumber = 1,
212+
.AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
213+
.AHBWriteWaitInterval = 0,
214+
.enableWriteMask = false,
215+
};
216+
FLEXSPI_SetFlashConfig(FLEXSPI2, &flexspi_device_config, kFLEXSPI_PortA1);
217+
FLEXSPI_SetFlashConfig(FLEXSPI2, &flexspi_device_config, kFLEXSPI_PortA2);
218+
219+
uint32_t cmd[64] = {0};
220+
// cmd index 0 = exit QPI mode
221+
cmd[0] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0xF5, 0, 0, 0);
222+
// cmd index 1 = reset enable
223+
cmd[4] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x66, 0, 0, 0);
224+
// cmd index 2 = reset
225+
cmd[8] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x99, 0, 0, 0);
226+
// cmd index 3 = read ID bytes
227+
cmd[12] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x9F, kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 24);
228+
cmd[13] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 1, 0, 0, 0);
229+
// cmd index 4 = enter QPI mode
230+
cmd[16] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x35, 0, 0, 0);
231+
// cmd index 5 = read QPI
232+
cmd[20] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0xEB, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 24);
233+
cmd[21] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 6, kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 1);
234+
// cmd index 6 = write QPI
235+
cmd[24] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_4PAD, 0x38, kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 24);
236+
cmd[25] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 1, 0, 0, 0);
237+
FLEXSPI_UpdateLUT(FLEXSPI2, 0, cmd, 64);
238+
239+
// Detected PSRAM size in MB
240+
uint8_t external_psram_size = 0;
241+
242+
// look for the first PSRAM chip
243+
uint8_t size1 = flexspi2_psram_size(0, kFLEXSPI_PortA1);
244+
if (size1 > 0) {
245+
flexspi_device_config.flashSize = size1 << 10;
246+
FLEXSPI_SetFlashConfig(FLEXSPI2, &flexspi_device_config, kFLEXSPI_PortA1);
247+
flexspi2_command(4, 0, kFLEXSPI_PortA1); // enter QPI mode
248+
// look for a second PSRAM chip
249+
uint8_t size2 = flexspi2_psram_size(size1 << 20, kFLEXSPI_PortA2);
250+
external_psram_size = size1 + size2;
251+
if (size2 > 0) {
252+
flexspi_device_config.flashSize = size2 << 10;
253+
FLEXSPI_SetFlashConfig(FLEXSPI2, &flexspi_device_config, kFLEXSPI_PortA2);
254+
flexspi2_command(4, size1 << 20, kFLEXSPI_PortA2); // enter QPI mode
255+
}
256+
} else {
257+
// No PSRAM
258+
external_psram_size = 0;
259+
}
260+
261+
// Return the size of the PSRAM in bytes
262+
return external_psram_size * 0x100000;
263+
}
264+
265+
#endif

‎ports/mimxrt/psram.h‎

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,36 @@
1+
/*
2+
* This file is part of the MicroPython project, http://micropython.org/
3+
*
4+
* The MIT License (MIT)
5+
*
6+
* Copyright (c) 2019 Paul Stoffregen
7+
* 2026 Dryw Wade
8+
*
9+
* Permission is hereby granted, free of charge, to any person obtaining a copy
10+
* of this software and associated documentation files (the "Software"), to deal
11+
* in the Software without restriction, including without limitation the rights
12+
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13+
* copies of the Software, and to permit persons to whom the Software is
14+
* furnished to do so, subject to the following conditions:
15+
*
16+
* The above copyright notice and this permission notice shall be included in
17+
* all copies or substantial portions of the Software.
18+
*
19+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
22+
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24+
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25+
* THE SOFTWARE.
26+
*/
27+
28+
#ifndef MICROPY_INCLUDED_MIMXRT_PSRAM_H
29+
#define MICROPY_INCLUDED_MIMXRT_PSRAM_H
30+
31+
#define PSRAM_BASE (0x70000000)
32+
33+
// Configures external PSRAM if available, returns size in bytes (0 if none).
34+
size_t configure_external_ram();
35+
36+
#endif // MICROPY_INCLUDED_MIMXRT_PSRAM_H

0 commit comments

Comments
 (0)