.github/workflows/ports_psoc6.yml: Update to run all ci tests.

Signed-off-by: NikhitaR-IFX <Nikhita.Rajasekhar@infineon.com>

Author: NikhitaR-IFX

.github/workflows/ports_psoc6.yml

@@ -72,15 +72,14 @@ jobs:
       timeout-minutes: 12
       run: |
        ./tests/ports/psoc6/run_psoc6_tests.sh --test-suite ci-tests --board ${{ matrix.board }} --hil ${{ runner.name }}
-#./tests/ports/psoc6/run_psoc6_tests.sh --test-suite pdm_pcm --board ${{ matrix.board }} --hil ${{ runner.name }} 
 
     - name: Container teardown 
       if: failure() || success()
       run: |
         source tools/ci.sh && ci_psoc6_teardown
 
   release:
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-latests
     needs: [server-build, on-target-test]
     strategy:
       matrix:

ports/psoc6/machine_pdm_pcm.c

@@ -461,7 +461,27 @@ static void mp_machine_pdm_pcm_init_helper(machine_pdm_pcm_obj_t *self, mp_arg_v
 
     // Set sampling and decimation rates (as given by user)
     self->sample_rate = args[ARG_sample_rate].u_int;
+
+    if (self->sample_rate == 8000 ||
+        self->sample_rate == 16000 ||
+        self->sample_rate == 32000 ||
+        self->sample_rate == 48000) {
+        if (PLL0_freq != AUDIO_PDM_24_576_000_HZ) {
+            mp_raise_ValueError(MP_ERROR_TEXT("Invalid clock frequency set for the sample rate/ PDM_PCM Clock not set . Set the right clock before initialising PDM_PCM"));
+        }
+    } else if (self->sample_rate == 22050 ||
+               self->sample_rate == 44100) {
+        if (PLL0_freq != AUDIO_PDM_22_579_000_HZ) {
+            mp_raise_ValueError(MP_ERROR_TEXT("Invalid clock frequency set for the sample rate/ PDM_PCM Clock not set. Set the right clock before initialising PDM_PCM"));
+        }
+    } else {
+        mp_raise_ValueError(MP_ERROR_TEXT("rate not supported"));
+    }
+
     self->decimation_rate = args[ARG_decimation_rate].u_int;
+    if (self->decimation_rate < 0) {
+        mp_raise_ValueError(MP_ERROR_TEXT("invalid decimation rate"));
+    }
 
     int32_t ring_buffer_len = 20000;
     if (ring_buffer_len < 0) {

tests/ports/psoc6/run_psoc6_tests.sh

@@ -272,9 +272,12 @@ run_ci_tests() {
     devs=($(python ${tools_psoc6_dir}/get-devs.py port -b ${board} -y ${tools_psoc6_dir}/${hil_name}-devs.yml))
 
     # TODO: This mess needs to be solved in a future script rework using yml files to define the compatible boards requirements
-    board_version=0.5.0
     if [ "${board}" == "CY8CKIT-062S2-AI" ]; then
       board_version=0.1.0
+    elif [ "${board}" == "CY8CPROTO-062-4343W" ]; then
+      board_version=0.6.0
+    elif [ "${board}" == "CY8CPROTO-063-BLE" ]; then
+      board_version=0.5.0
     fi
 
     devs_a=($(python ${tools_psoc6_dir}/get-devs.py port -b ${board} -y ${tools_psoc6_dir}/${hil_name}-devs.yml --hw-ext ${board_version}.a))

tools/psoc6/ifx-mpy-hil-devs.yml

@@ -1,9 +1,9 @@
 - board_type: CY8CPROTO-062-4343W
   board_list:
     - sn: 072002F302098400
-      hw_ext: 0.5.0.a
+      hw_ext: 0.6.0.a
     - sn: 1C14031D03201400
-      hw_ext: 0.5.0.b
+      hw_ext: 0.6.0.b
 - board_type: CY8CPROTO-063-BLE
   board_list:
     - sn: 100D0F1400052400