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tests/ports/psoc6/../pdm_pcm: Refactored to use interrupt synch.
Signed-off-by: enriquezgarc <enriquezgarcia.external@infineon.com>
1 parent 1122f9b commit 7b7703b

2 files changed

Lines changed: 10 additions & 18 deletions

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tests/ports/psoc6/board_ext_hw/multi/pdm_pcm_rx.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,6 @@
1919
print("*** PDM_PCM tests - RX ***")
2020

2121
send_signal = Pin(send_signal_to_tx_pin, mode=Pin.OUT, pull=Pin.PULL_DOWN, value=False)
22-
send_signal.value(0)
2322

2423

2524
def generate_exp_seq(data):
@@ -37,6 +36,7 @@ def generate_exp_seq(data):
3736
rounds = 2
3837

3938
for m in range(rounds):
39+
send_signal.value(0)
4040
exp_seq = generate_exp_seq(exp_data[m])
4141
if m == 0:
4242
print("*** Test for data high ***")
@@ -94,7 +94,7 @@ def rx_complete_irq(obj):
9494
rx_done = True
9595

9696

97-
machine.freq(machine.AUDIO_PDM_24_576_000_HZ)
97+
machine.freq(machine.AUDIO_PDM_22_579_000_HZ)
9898
pdm_pcm = PDM_PCM(
9999
0,
100100
sck=clk_pin,

tests/ports/psoc6/board_ext_hw/multi/pdm_pcm_tx.py

Lines changed: 8 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -15,21 +15,13 @@
1515
print("SKIP")
1616
raise SystemExit
1717

18-
start_time = time.time()
19-
20-
sig_val = 1
18+
sig_val = 0
2119
test_done = False
2220

2321

2422
def signal_irq(event):
2523
global sig_val
26-
sig_val = 0
27-
28-
29-
def blocking_delay_ms(delay_ms):
30-
start = time.ticks_ms()
31-
while time.ticks_diff(time.ticks_ms(), start) < delay_ms:
32-
pass
24+
sig_val += 1
3325

3426

3527
data_out = Pin(data_out_pin, mode=Pin.OUT, pull=Pin.PULL_DOWN, value=False)
@@ -38,12 +30,12 @@ def blocking_delay_ms(delay_ms):
3830
sync_data.irq(handler=signal_irq, trigger=Pin.IRQ_RISING)
3931

4032
data_out.value(1)
41-
while test_done == False:
42-
while sig_val:
43-
pass
44-
data_out.value(0)
45-
blocking_delay_ms(200000)
46-
test_done = True
33+
while sig_val == 0:
34+
pass
35+
36+
data_out.value(0)
37+
while sig_val == 1:
38+
pass
4739

4840
data_out.deinit()
4941
clk_in.deinit()

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