ports/psoc6: Fix clock change msg.

Signed-off-by: NikhitaR-IFX <Nikhita.Rajasekhar@infineon.com>

Author: NikhitaR-IFX

ports/psoc6/machine_i2s.c

@@ -115,7 +115,7 @@ void i2s_audio_clock_init(uint32_t audio_clock_freq_hz) {
     uint32_t pll_source_clock_freq_hz = cyhal_clock_get_frequency(&clock_pll);
 
     if (audio_clock_freq_hz != pll_source_clock_freq_hz) {
-        mp_printf(&mp_plat_print, "machine.I2S: PLL0 freq is changed from %lu to %lu. This will affect all resources clock freq sourced by PLL0.\n", pll_source_clock_freq_hz, audio_clock_freq_hz);
+        mp_printf(&mp_plat_print, "machine.I2S: PLL0 freq is changed to %lu. This will affect all resources clock freq sourced by PLL0.\n", audio_clock_freq_hz);
         clock_set = false;
         pll_source_clock_freq_hz = audio_clock_freq_hz;
     }

ports/psoc6/machine_pdm_pcm.c

@@ -186,7 +186,7 @@ void pdm_pcm_audio_clock_init(uint32_t audio_clock_freq_hz) {
     uint32_t pll_source_clock_freq_hz = cyhal_clock_get_frequency(&pll_clock);
 
     if (audio_clock_freq_hz != pll_source_clock_freq_hz) {
-        mp_printf(&mp_plat_print, "machine.PDM_PCM: PLL0 freq is changed from %lu to %lu. This will affect all resources clock freq sourced by PLL0.\n", pll_source_clock_freq_hz, audio_clock_freq_hz);
+        mp_printf(&mp_plat_print, "machine.PDM_PCM: PLL0 freq is changed to %lu. This will affect all resources clock freq sourced by PLL0.\n", audio_clock_freq_hz);
         clock_set = false;
         pll_source_clock_freq_hz = audio_clock_freq_hz;
     }

tests/ports/psoc6/board_ext_hw/multi/i2s_rx.py.exp

@@ -1,39 +1,39 @@
 1. tx-rx data for all formats, rates and bit resolution
-machine.I2S: PLL0 freq is changed from 48000000 to 98000000. This will affect all resources clock freq sourced by PLL0.
+machine.I2S: PLL0 freq is changed to 98000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 0, bits = 16, rate = 8000 : True
 data received for format = 0, bits = 16, rate = 16000 : True
 data received for format = 0, bits = 16, rate = 32000 : True
 data received for format = 0, bits = 16, rate = 48000 : True
-machine.I2S: PLL0 freq is changed from 98000000 to 90000000. This will affect all resources clock freq sourced by PLL0.
+machine.I2S: PLL0 freq is changed to 90000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 0, bits = 16, rate = 22050 : True
 data received for format = 0, bits = 16, rate = 44100 : True
-machine.I2S: PLL0 freq is changed from 90000000 to 98000000. This will affect all resources clock freq sourced by PLL0.
+machine.I2S: PLL0 freq is changed to 98000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 0, bits = 32, rate = 8000 : True
 data received for format = 0, bits = 32, rate = 16000 : True
 data received for format = 0, bits = 32, rate = 32000 : True
 data received for format = 0, bits = 32, rate = 48000 : True
-machine.I2S: PLL0 freq is changed from 98000000 to 90000000. This will affect all resources clock freq sourced by PLL0.
+machine.I2S: PLL0 freq is changed to 90000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 0, bits = 32, rate = 22050 : True
 data received for format = 0, bits = 32, rate = 44100 : True
-machine.I2S: PLL0 freq is changed from 90000000 to 98000000. This will affect all resources clock freq sourced by PLL0.
+machine.I2S: PLL0 freq is changed to 98000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 1, bits = 16, rate = 8000 : True
 data received for format = 1, bits = 16, rate = 16000 : True
 data received for format = 1, bits = 16, rate = 32000 : True
 data received for format = 1, bits = 16, rate = 48000 : True
-machine.I2S: PLL0 freq is changed from 98000000 to 90000000. This will affect all resources clock freq sourced by PLL0.
+machine.I2S: PLL0 freq is changed to 90000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 1, bits = 16, rate = 22050 : True
 data received for format = 1, bits = 16, rate = 44100 : True
-machine.I2S: PLL0 freq is changed from 90000000 to 98000000. This will affect all resources clock freq sourced by PLL0.
+machine.I2S: PLL0 freq is changed to 98000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 1, bits = 32, rate = 8000 : True
 data received for format = 1, bits = 32, rate = 16000 : True
 data received for format = 1, bits = 32, rate = 32000 : True
 data received for format = 1, bits = 32, rate = 48000 : True
-machine.I2S: PLL0 freq is changed from 98000000 to 90000000. This will affect all resources clock freq sourced by PLL0.
+machine.I2S: PLL0 freq is changed to 90000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 1, bits = 32, rate = 22050 : True
 data received for format = 1, bits = 32, rate = 44100 : True
 
 2. irq non-blocking read implementation 
-machine.I2S: PLL0 freq is changed from 90000000 to 98000000. This will affect all resources clock freq sourced by PLL0.
+machine.I2S: PLL0 freq is changed to 98000000. This will affect all resources clock freq sourced by PLL0.
 rx blocking done
 
 3. shift 

tests/ports/psoc6/board_ext_hw/multi/pdm_pcm.py

@@ -6,11 +6,9 @@
 if "CY8CPROTO-062-4343W" in board:
     clk_pin = "P10_4"
     data_pin = "P10_5"
-
 elif "CY8CPROTO-063-BLE" in board:
     print("SKIP")
     raise SystemExit
-
 elif "CY8CKIT-062S2-AI" in board:
     clk_pin = "P10_4"
     data_pin = "P10_5"

tests/ports/psoc6/board_ext_hw/multi/pdm_pcm.py.exp

@@ -1 +1 @@
-machine.PDM_PCM: PLL0 freq is changed from 48000000 to 24576000. This will affect all resources clock freq sourced by PLL0.
+machine.PDM_PCM: PLL0 freq is changed to 24576000. This will affect all resources clock freq sourced by PLL0.