tests/ports/psoc6: Add small delay to avoid sig gen issues.

NikhitaR-IFX · NikhitaR-IFX · commit b425f2dbc926 · 2025-07-21T12:27:54.000+05:30
Signed-off-by: NikhitaR-IFX &lt;nikhita.rajasekhar@infineon.com&gt;
diff --git a/tests/ports/psoc6/board_ext_hw/single/time_pulse_us.py b/tests/ports/psoc6/board_ext_hw/single/time_pulse_us.py
@@ -27,12 +27,14 @@
 )
 
 pwm.duty_ns(500000000)
+time.sleep(0.5)
 width = time_pulse_us(pulse_in, 1, 1000000)
 print(
     f"Pulse timing verified for 50% dc : {True if (0.45 < (width / 1000000) < 0.55) else 'False, width=' + str(width / 1000000)}"
 )
 
 pwm.duty_ns(750000000)
+time.sleep(0.5)
 width = time_pulse_us(pulse_in, 1, 1000000)
 print(
     f"Pulse timing verified for 75% dc : {True if (0.70 < (width / 1000000) < 0.80) else 'False, width=' + str(width / 1000000)}"

Original file line number	Diff line number	Diff line change
`@@ -27,12 +27,14 @@`
`27`	`27`	`)`
`28`	`28`
`29`	`29`	`pwm.duty_ns(500000000)`
	`30`	`+time.sleep(0.5)`
`30`	`31`	`width = time_pulse_us(pulse_in, 1, 1000000)`
`31`	`32`	`print(`
`32`	`33`	`f"Pulse timing verified for 50% dc : {True if (0.45 < (width / 1000000) < 0.55) else 'False, width=' + str(width / 1000000)}"`
`33`	`34`	`)`
`34`	`35`
`35`	`36`	`pwm.duty_ns(750000000)`
	`37`	`+time.sleep(0.5)`
`36`	`38`	`width = time_pulse_us(pulse_in, 1, 1000000)`
`37`	`39`	`print(`
`38`	`40`	`f"Pulse timing verified for 75% dc : {True if (0.70 < (width / 1000000) < 0.80) else 'False, width=' + str(width / 1000000)}"`