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Merge tag 'renesas-clk-for-v6.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven: - Various fixes for the module reset procedure on R-Car Gen4 SoCs - Add ADC and thermal (TSU) clocks on RZ/T2H and RZ/N2H - Add USB clocks and resets on RZ/G3E - Add ISP and display (DSI, LCDC) clocks and resets on RZ/V2H and RZ/V2N - Add thermal (TSU) and RTC clocks and resets on RZ/V2H - Add reset support on RZ/T2H and RZ/N2H - Fix the module stop disable procedure on RZ/T2H and RZ/N2H - Add camera (CRU) clocks and resets on RZ/V2N * tag 'renesas-clk-for-v6.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (21 commits) clk: renesas: r9a09g056: Add clock and reset entries for ISP clk: renesas: r9a09g056: Add support for PLLVDO, CRU clocks, and resets clk: renesas: r9a09g056: Add clocks and resets for DSI and LCDC modules clk: renesas: r9a09g077: Add TSU module clock clk: renesas: r9a09g057: Add clock and reset entries for DSI and LCDC clk: renesas: rzv2h: Add support for DSI clocks clk: renesas: rzv2h: Use GENMASK for PLL fields clk: renesas: rzv2h: Add instance field to struct pll clk: renesas: r9a09g057: Add clock and reset entries for RTC clk: renesas: cpg-mssr: Spelling s/offets/offsets/ clk: renesas: r9a09g057: Add clock and reset entries for TSU clk: renesas: cpg-mssr: Add read-back and delay handling for RZ/T2H MSTP clk: renesas: cpg-mssr: Add module reset support for RZ/T2H clk: renesas: r9a09g057: Add clock and reset entries for ISP clk: renesas: r9a09g047: Add clock and reset entries for USB2 clk: renesas: Use IS_ERR() for pointers that cannot be NULL dt-bindings: clock: renesas,r9a09g047-cpg: Add USB2 PHY core clocks clk: renesas: cpg-lib: Remove unneeded semicolon clk: renesas: r9a09g077: Add ADC module clocks clk: renesas: cpg-mssr: Read back reset registers to assure values latched ...
2 parents 3a86608 + 07525a6 commit 1f2d68c

11 files changed

Lines changed: 1047 additions & 47 deletions

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‎drivers/clk/renesas/r9a09g047-cpg.c‎

Lines changed: 17 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616

1717
enum clk_ids {
1818
/* Core Clock Outputs exported to DT */
19-
LAST_DT_CORE_CLK = R9A09G047_USB3_0_CLKCORE,
19+
LAST_DT_CORE_CLK = R9A09G047_USB2_0_CLK_CORE1,
2020

2121
/* External Input Clocks */
2222
CLK_AUDIO_EXTAL,
@@ -177,6 +177,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
177177
CDDIV1_DIVCTL3, dtable_1_8),
178178
DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
179179
DEF_FIXED("spi_clk_spi", R9A09G047_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2),
180+
DEF_FIXED("usb2_0_clk_core0", R9A09G047_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1),
181+
DEF_FIXED("usb2_0_clk_core1", R9A09G047_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1),
180182
DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G047_GBETH_0_CLK_PTP_REF_I,
181183
CLK_PLLETH_DIV_125_FIX, 1, 1),
182184
DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G047_GBETH_1_CLK_PTP_REF_I,
@@ -282,6 +284,16 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
282284
BUS_MSTOP(7, BIT(12))),
283285
DEF_MOD("usb3_0_pclk_usbtst", CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,
284286
BUS_MSTOP(7, BIT(14))),
287+
DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19,
288+
BUS_MSTOP(7, BIT(7))),
289+
DEF_MOD("usb2_0_u2h1_hclk", CLK_PLLDTY_DIV8, 11, 4, 5, 20,
290+
BUS_MSTOP(7, BIT(8))),
291+
DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
292+
BUS_MSTOP(7, BIT(9))),
293+
DEF_MOD("usb2_0_pclk_usbtst0", CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,
294+
BUS_MSTOP(7, BIT(10))),
295+
DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23,
296+
BUS_MSTOP(7, BIT(11))),
285297
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
286298
BUS_MSTOP(8, BIT(5)), 1),
287299
DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
@@ -359,6 +371,10 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
359371
DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */
360372
DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
361373
DEF_RST(10, 10, 4, 27), /* USB3_0_ARESETN */
374+
DEF_RST(10, 12, 4, 29), /* USB2_0_U2H0_HRESETN */
375+
DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */
376+
DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */
377+
DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
362378
DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
363379
DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
364380
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */

‎drivers/clk/renesas/r9a09g056-cpg.c‎

Lines changed: 109 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
*/
77

88
#include <linux/clk-provider.h>
9+
#include <linux/clk/renesas.h>
910
#include <linux/device.h>
1011
#include <linux/init.h>
1112
#include <linux/kernel.h>
@@ -28,7 +29,9 @@ enum clk_ids {
2829
CLK_PLLCLN,
2930
CLK_PLLDTY,
3031
CLK_PLLCA55,
32+
CLK_PLLVDO,
3133
CLK_PLLETH,
34+
CLK_PLLDSI,
3235
CLK_PLLGPU,
3336

3437
/* Internal Core Clocks */
@@ -47,6 +50,10 @@ enum clk_ids {
4750
CLK_PLLDTY_ACPU_DIV2,
4851
CLK_PLLDTY_ACPU_DIV4,
4952
CLK_PLLDTY_DIV8,
53+
CLK_PLLDTY_DIV16,
54+
CLK_PLLVDO_CRU0,
55+
CLK_PLLVDO_CRU1,
56+
CLK_PLLVDO_ISP,
5057
CLK_PLLETH_DIV_250_FIX,
5158
CLK_PLLETH_DIV_125_FIX,
5259
CLK_CSDIV_PLLETH_GBE0,
@@ -55,6 +62,9 @@ enum clk_ids {
5562
CLK_SMUX2_GBE0_RXCLK,
5663
CLK_SMUX2_GBE1_TXCLK,
5764
CLK_SMUX2_GBE1_RXCLK,
65+
CLK_CDIV4_PLLETH_LPCLK,
66+
CLK_PLLETH_LPCLK_GEAR,
67+
CLK_PLLDSI_GEAR,
5868
CLK_PLLGPU_GEAR,
5969

6070
/* Module Clocks */
@@ -69,6 +79,12 @@ static const struct clk_div_table dtable_1_8[] = {
6979
{0, 0},
7080
};
7181

82+
static const struct clk_div_table dtable_2_4[] = {
83+
{0, 2},
84+
{1, 4},
85+
{0, 0},
86+
};
87+
7288
static const struct clk_div_table dtable_2_16[] = {
7389
{0, 2},
7490
{1, 4},
@@ -77,6 +93,26 @@ static const struct clk_div_table dtable_2_16[] = {
7793
{0, 0},
7894
};
7995

96+
static const struct clk_div_table dtable_2_32[] = {
97+
{0, 2},
98+
{1, 4},
99+
{2, 6},
100+
{3, 8},
101+
{4, 10},
102+
{5, 12},
103+
{6, 14},
104+
{7, 16},
105+
{8, 18},
106+
{9, 20},
107+
{10, 22},
108+
{11, 24},
109+
{12, 26},
110+
{13, 28},
111+
{14, 30},
112+
{15, 32},
113+
{0, 0},
114+
};
115+
80116
static const struct clk_div_table dtable_2_64[] = {
81117
{0, 2},
82118
{1, 4},
@@ -93,6 +129,17 @@ static const struct clk_div_table dtable_2_100[] = {
93129
{0, 0},
94130
};
95131

132+
static const struct clk_div_table dtable_16_128[] = {
133+
{0, 16},
134+
{1, 32},
135+
{2, 64},
136+
{3, 128},
137+
{0, 0},
138+
};
139+
140+
RZV2H_CPG_PLL_DSI_LIMITS(rzv2n_cpg_pll_dsi_limits);
141+
#define PLLDSI PLL_PACK_LIMITS(0xc0, 1, 0, &rzv2n_cpg_pll_dsi_limits)
142+
96143
/* Mux clock tables */
97144
static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
98145
static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
@@ -112,7 +159,9 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
112159
DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
113160
DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
114161
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
162+
DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
115163
DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
164+
DEF_PLLDSI(".plldsi", CLK_PLLDSI, CLK_QEXTAL, PLLDSI),
116165
DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU),
117166

118167
/* Internal Core Clocks */
@@ -134,6 +183,11 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
134183
DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
135184
DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
136185
DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),
186+
DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
187+
188+
DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
189+
DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4),
190+
DEF_DDIV(".pllvdo_isp", CLK_PLLVDO_ISP, CLK_PLLVDO, CDDIV2_DIVCTL3, dtable_2_64),
137191

138192
DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),
139193
DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
@@ -145,6 +199,12 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
145199
DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),
146200
DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),
147201
DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),
202+
DEF_FIXED(".cdiv4_plleth_lpclk", CLK_CDIV4_PLLETH_LPCLK, CLK_PLLETH, 1, 4),
203+
DEF_CSDIV(".plleth_lpclk_gear", CLK_PLLETH_LPCLK_GEAR, CLK_CDIV4_PLLETH_LPCLK,
204+
CSDIV0_DIVCTL2, dtable_16_128),
205+
206+
DEF_PLLDSI_DIV(".plldsi_gear", CLK_PLLDSI_GEAR, CLK_PLLDSI,
207+
CSDIV1_DIVCTL2, dtable_2_32),
148208

149209
DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
150210

@@ -289,6 +349,42 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
289349
BUS_MSTOP(8, BIT(6))),
290350
DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
291351
BUS_MSTOP(8, BIT(6))),
352+
DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
353+
BUS_MSTOP(9, BIT(4))),
354+
DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
355+
BUS_MSTOP(9, BIT(4))),
356+
DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
357+
BUS_MSTOP(9, BIT(4))),
358+
DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21,
359+
BUS_MSTOP(9, BIT(5))),
360+
DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22,
361+
BUS_MSTOP(9, BIT(5))),
362+
DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23,
363+
BUS_MSTOP(9, BIT(5))),
364+
DEF_MOD("isp_0_reg_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 2, 7, 2,
365+
BUS_MSTOP(9, BIT(8))),
366+
DEF_MOD("isp_0_pclk", CLK_PLLDTY_DIV16, 14, 3, 7, 3,
367+
BUS_MSTOP(9, BIT(8))),
368+
DEF_MOD("isp_0_vin_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 4, 7, 4,
369+
BUS_MSTOP(9, BIT(9))),
370+
DEF_MOD("isp_0_isp_sclk", CLK_PLLVDO_ISP, 14, 5, 7, 5,
371+
BUS_MSTOP(9, BIT(9))),
372+
DEF_MOD("dsi_0_pclk", CLK_PLLDTY_DIV16, 14, 8, 7, 8,
373+
BUS_MSTOP(9, BIT(14) | BIT(15))),
374+
DEF_MOD("dsi_0_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 9, 7, 9,
375+
BUS_MSTOP(9, BIT(14) | BIT(15))),
376+
DEF_MOD("dsi_0_vclk1", CLK_PLLDSI_GEAR, 14, 10, 7, 10,
377+
BUS_MSTOP(9, BIT(14) | BIT(15))),
378+
DEF_MOD("dsi_0_lpclk", CLK_PLLETH_LPCLK_GEAR, 14, 11, 7, 11,
379+
BUS_MSTOP(9, BIT(14) | BIT(15))),
380+
DEF_MOD("dsi_0_pllref_clk", CLK_QEXTAL, 14, 12, 7, 12,
381+
BUS_MSTOP(9, BIT(14) | BIT(15))),
382+
DEF_MOD("lcdc_0_clk_a", CLK_PLLDTY_ACPU_DIV2, 14, 13, 7, 13,
383+
BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
384+
DEF_MOD("lcdc_0_clk_p", CLK_PLLDTY_DIV16, 14, 14, 7, 14,
385+
BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
386+
DEF_MOD("lcdc_0_clk_d", CLK_PLLDSI_GEAR, 14, 15, 7, 15,
387+
BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),
292388
DEF_MOD("gpu_0_clk", CLK_PLLGPU_GEAR, 15, 0, 7, 16,
293389
BUS_MSTOP(3, BIT(4))),
294390
DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
@@ -335,6 +431,19 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
335431
DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
336432
DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
337433
DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
434+
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
435+
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
436+
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
437+
DEF_RST(12, 8, 5, 25), /* CRU_1_PRESETN */
438+
DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */
439+
DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */
440+
DEF_RST(13, 1, 6, 2), /* ISP_0_VIN_ARESETN */
441+
DEF_RST(13, 2, 6, 3), /* ISP_0_REG_ARESETN */
442+
DEF_RST(13, 3, 6, 4), /* ISP_0_ISP_SRESETN */
443+
DEF_RST(13, 4, 6, 5), /* ISP_0_PRESETN */
444+
DEF_RST(13, 7, 6, 8), /* DSI_0_PRESETN */
445+
DEF_RST(13, 8, 6, 9), /* DSI_0_ARESETN */
446+
DEF_RST(13, 12, 6, 13), /* LCDC_0_RESET_N */
338447
DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */
339448
DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */
340449
DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */

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