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Merge tag 'clk-microchip-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip
Pull Microchip clk driver updates from Claudiu Beznea: Microchip AT91: - add generic clocks for U(S)ART available on SAMA5D2 SoCs Microchip Polarfire: - reset controller support for Polarfire clocks - .round_rate and .set rate support for clk-mpfs - code cleanup for clk-mpfs - PLL support for PolarFire SoC's Clock Conditioning Circuitry * tag 'clk-microchip-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: clk: at91: sama5d2: Add Generic Clocks for UART/USART clk: microchip: add PolarFire SoC fabric clock support dt-bindings: clk: add PolarFire SoC fabric clock ids dt-bindings: clk: document PolarFire SoC fabric clocks dt-bindings: clk: rename mpfs-clkcfg binding clk: microchip: mpfs: update module authorship & licencing clk: microchip: mpfs: convert periph_clk to clk_gate clk: microchip: mpfs: convert cfg_clk to clk_divider clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo() clk: microchip: mpfs: simplify control reg access clk: microchip: mpfs: move id & offset out of clock structs clk: microchip: mpfs: add MSS pll's set & round rate MAINTAINERS: add polarfire soc reset controller reset: add polarfire soc reset support clk: microchip: mpfs: add reset controller dt-bindings: clk: microchip: mpfs: add reset controller support clk: microchip: mpfs: make the rtc's ahb clock critical clk: microchip: mpfs: fix clk_cfg array bounds violation
2 parents 568035b + 935edf0 commit 50cf94b

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‎Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry
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maintainers:
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- Conor Dooley <conor.dooley@microchip.com>
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description: |
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Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of
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these blocks contains two PLLs and 2 DLLs & are located in the four corners of
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the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at:
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https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
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properties:
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compatible:
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const: microchip,mpfs-ccc
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reg:
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items:
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- description: PLL0's control registers
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- description: PLL1's control registers
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- description: DLL0's control registers
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- description: DLL1's control registers
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clocks:
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description:
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The CCC PLL's have two input clocks. It is required that even if the input
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clocks are identical that both are provided.
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minItems: 2
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items:
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- description: PLL0's refclk0
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- description: PLL0's refclk1
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- description: PLL1's refclk0
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- description: PLL1's refclk1
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- description: DLL0's refclk
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- description: DLL1's refclk
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clock-names:
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minItems: 2
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items:
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- const: pll0_ref0
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- const: pll0_ref1
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- const: pll1_ref0
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- const: pll1_ref1
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- const: dll0_ref
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- const: dll1_ref
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'#clock-cells':
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const: 1
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description: |
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell.
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See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
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PolarFire clock IDs.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@38100000 {
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compatible = "microchip,mpfs-ccc";
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reg = <0x38010000 0x1000>, <0x38020000 0x1000>,
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<0x39010000 0x1000>, <0x39020000 0x1000>;
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#clock-cells = <1>;
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clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
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<&refclk_ccc>, <&refclk_ccc>;
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clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
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"dll0_ref", "dll1_ref";
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};

Documentation/devicetree/bindings/clock/microchip,mpfs.yaml renamed to Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/microchip,mpfs.yaml#
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$id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip PolarFire Clock Control Module Binding
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const: 1
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description: |
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h
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for the full list of PolarFire clock IDs.
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ID in its "clocks" phandle cell.
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See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
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PolarFire clock IDs.
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resets:
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maxItems: 1
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'#reset-cells':
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description:
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The AHB/AXI peripherals on the PolarFire SoC have reset support, so from
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CLK_ENVM to CLK_CFM. The reset consumer should specify the desired
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peripheral via the clock ID in its "resets" phandle cell.
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See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
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PolarFire clock IDs.
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const: 1
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required:
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- compatible

‎MAINTAINERS‎

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F: drivers/clk/microchip/clk-mpfs.c
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F: drivers/mailbox/mailbox-mpfs.c
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F: drivers/pci/controller/pcie-microchip-host.c
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F: drivers/reset/reset-mpfs.c
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F: drivers/rtc/rtc-mpfs.c
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F: drivers/soc/microchip/
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F: drivers/spi/spi-microchip-core.c

‎drivers/clk/at91/sama5d2.c‎

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struct clk_range r;
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int chg_pid;
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} sama5d2_gck[] = {
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{ .n = "flx0_gclk", .id = 19, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
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{ .n = "flx1_gclk", .id = 20, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
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{ .n = "flx2_gclk", .id = 21, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
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{ .n = "flx3_gclk", .id = 22, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
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{ .n = "flx4_gclk", .id = 23, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
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{ .n = "uart0_gclk", .id = 24, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
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{ .n = "uart1_gclk", .id = 25, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
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{ .n = "uart2_gclk", .id = 26, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
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{ .n = "uart3_gclk", .id = 27, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
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{ .n = "uart4_gclk", .id = 28, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
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{ .n = "sdmmc0_gclk", .id = 31, .chg_pid = INT_MIN, },
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{ .n = "sdmmc1_gclk", .id = 32, .chg_pid = INT_MIN, },
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{ .n = "tcb0_gclk", .id = 35, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },

‎drivers/clk/microchip/Kconfig‎

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config MCHP_CLK_MPFS
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bool "Clk driver for PolarFire SoC"
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depends on (RISCV && SOC_MICROCHIP_POLARFIRE) || COMPILE_TEST
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select AUXILIARY_BUS
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help
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Supports Clock Configuration for PolarFire SoC

‎drivers/clk/microchip/Makefile‎

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obj-$(CONFIG_COMMON_CLK_PIC32) += clk-core.o
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obj-$(CONFIG_PIC32MZDA) += clk-pic32mzda.o
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obj-$(CONFIG_MCHP_CLK_MPFS) += clk-mpfs.o
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obj-$(CONFIG_MCHP_CLK_MPFS) += clk-mpfs-ccc.o

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