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taniyadas20andersson
taniyadas20
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clk: qcom: ecpricc-qdu100: Add mem_enable_mask to the clock memory branch
The ECPRI clock controller’s mem_ops clocks used the mem_enable_ack_mask directly for both setting and polling. Add the newly introduced 'mem_enable_mask' to the memory control branch clocks of ECPRI clock controller to align to the new mem_ops handling. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251118-sm8750-videocc-v2-v4-2-049882a70c9f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
1 parent 165d0b6 commit 53a1895

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‎drivers/clk/qcom/ecpricc-qdu1000.c‎

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -920,6 +920,7 @@ static struct clk_branch ecpri_cc_eth_100g_c2c1_udp_fifo_clk = {
920920
static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_0_clk = {
921921
.mem_enable_reg = 0x8410,
922922
.mem_ack_reg = 0x8424,
923+
.mem_enable_mask = BIT(0),
923924
.mem_enable_ack_mask = BIT(0),
924925
.branch = {
925926
.halt_reg = 0x80b4,
@@ -943,6 +944,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_0_clk = {
943944
static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_1_clk = {
944945
.mem_enable_reg = 0x8410,
945946
.mem_ack_reg = 0x8424,
947+
.mem_enable_mask = BIT(1),
946948
.mem_enable_ack_mask = BIT(1),
947949
.branch = {
948950
.halt_reg = 0x80bc,
@@ -966,6 +968,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_1_clk = {
966968
static struct clk_mem_branch ecpri_cc_eth_100g_c2c_hm_macsec_clk = {
967969
.mem_enable_reg = 0x8410,
968970
.mem_ack_reg = 0x8424,
971+
.mem_enable_mask = BIT(4),
969972
.mem_enable_ack_mask = BIT(4),
970973
.branch = {
971974
.halt_reg = 0x80ac,
@@ -989,6 +992,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_c2c_hm_macsec_clk = {
989992
static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_clk = {
990993
.mem_enable_reg = 0x8414,
991994
.mem_ack_reg = 0x8428,
995+
.mem_enable_mask = BIT(0),
992996
.mem_enable_ack_mask = BIT(0),
993997
.branch = {
994998
.halt_reg = 0x80d8,
@@ -1012,6 +1016,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_clk = {
10121016
static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_clk = {
10131017
.mem_enable_reg = 0x8414,
10141018
.mem_ack_reg = 0x8428,
1019+
.mem_enable_mask = BIT(1),
10151020
.mem_enable_ack_mask = BIT(1),
10161021
.branch = {
10171022
.halt_reg = 0x80e0,
@@ -1053,6 +1058,7 @@ static struct clk_branch ecpri_cc_eth_100g_dbg_c2c_udp_fifo_clk = {
10531058
static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_0_clk = {
10541059
.mem_enable_reg = 0x8404,
10551060
.mem_ack_reg = 0x8418,
1061+
.mem_enable_mask = BIT(0),
10561062
.mem_enable_ack_mask = BIT(0),
10571063
.branch = {
10581064
.halt_reg = 0x800c,
@@ -1076,6 +1082,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_0_clk = {
10761082
static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_1_clk = {
10771083
.mem_enable_reg = 0x8404,
10781084
.mem_ack_reg = 0x8418,
1085+
.mem_enable_mask = BIT(1),
10791086
.mem_enable_ack_mask = BIT(1),
10801087
.branch = {
10811088
.halt_reg = 0x8014,
@@ -1099,6 +1106,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_1_clk = {
10991106
static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_2_clk = {
11001107
.mem_enable_reg = 0x8404,
11011108
.mem_ack_reg = 0x8418,
1109+
.mem_enable_mask = BIT(2),
11021110
.mem_enable_ack_mask = BIT(2),
11031111
.branch = {
11041112
.halt_reg = 0x801c,
@@ -1122,6 +1130,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_2_clk = {
11221130
static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_3_clk = {
11231131
.mem_enable_reg = 0x8404,
11241132
.mem_ack_reg = 0x8418,
1133+
.mem_enable_mask = BIT(3),
11251134
.mem_enable_ack_mask = BIT(3),
11261135
.branch = {
11271136
.halt_reg = 0x8024,
@@ -1163,6 +1172,7 @@ static struct clk_branch ecpri_cc_eth_100g_fh_0_udp_fifo_clk = {
11631172
static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_0_clk = {
11641173
.mem_enable_reg = 0x8408,
11651174
.mem_ack_reg = 0x841c,
1175+
.mem_enable_mask = BIT(0),
11661176
.mem_enable_ack_mask = BIT(0),
11671177
.branch = {
11681178
.halt_reg = 0x8044,
@@ -1186,6 +1196,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_0_clk = {
11861196
static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_1_clk = {
11871197
.mem_enable_reg = 0x8408,
11881198
.mem_ack_reg = 0x841c,
1199+
.mem_enable_mask = BIT(1),
11891200
.mem_enable_ack_mask = BIT(1),
11901201
.branch = {
11911202
.halt_reg = 0x804c,
@@ -1209,6 +1220,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_1_clk = {
12091220
static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_2_clk = {
12101221
.mem_enable_reg = 0x8408,
12111222
.mem_ack_reg = 0x841c,
1223+
.mem_enable_mask = BIT(2),
12121224
.mem_enable_ack_mask = BIT(2),
12131225
.branch = {
12141226
.halt_reg = 0x8054,
@@ -1232,6 +1244,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_2_clk = {
12321244
static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_3_clk = {
12331245
.mem_enable_reg = 0x8408,
12341246
.mem_ack_reg = 0x841c,
1247+
.mem_enable_mask = BIT(3),
12351248
.mem_enable_ack_mask = BIT(3),
12361249
.branch = {
12371250
.halt_reg = 0x805c,
@@ -1273,6 +1286,7 @@ static struct clk_branch ecpri_cc_eth_100g_fh_1_udp_fifo_clk = {
12731286
static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_0_clk = {
12741287
.mem_enable_reg = 0x840c,
12751288
.mem_ack_reg = 0x8420,
1289+
.mem_enable_mask = BIT(0),
12761290
.mem_enable_ack_mask = BIT(0),
12771291
.branch = {
12781292
.halt_reg = 0x807c,
@@ -1296,6 +1310,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_0_clk = {
12961310
static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_1_clk = {
12971311
.mem_enable_reg = 0x840c,
12981312
.mem_ack_reg = 0x8420,
1313+
.mem_enable_mask = BIT(1),
12991314
.mem_enable_ack_mask = BIT(1),
13001315
.branch = {
13011316
.halt_reg = 0x8084,
@@ -1319,6 +1334,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_1_clk = {
13191334
static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_2_clk = {
13201335
.mem_enable_reg = 0x840c,
13211336
.mem_ack_reg = 0x8420,
1337+
.mem_enable_mask = BIT(2),
13221338
.mem_enable_ack_mask = BIT(2),
13231339
.branch = {
13241340
.halt_reg = 0x808c,
@@ -1342,6 +1358,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_2_clk = {
13421358
static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_3_clk = {
13431359
.mem_enable_reg = 0x840c,
13441360
.mem_ack_reg = 0x8420,
1361+
.mem_enable_mask = BIT(3),
13451362
.mem_enable_ack_mask = BIT(3),
13461363
.branch = {
13471364
.halt_reg = 0x8094,
@@ -1383,6 +1400,7 @@ static struct clk_branch ecpri_cc_eth_100g_fh_2_udp_fifo_clk = {
13831400
static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_0_clk = {
13841401
.mem_enable_reg = 0x8404,
13851402
.mem_ack_reg = 0x8418,
1403+
.mem_enable_mask = BIT(4),
13861404
.mem_enable_ack_mask = BIT(4),
13871405
.branch = {
13881406
.halt_reg = 0x8004,
@@ -1406,6 +1424,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_0_clk = {
14061424
static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_1_clk = {
14071425
.mem_enable_reg = 0x8408,
14081426
.mem_ack_reg = 0x841c,
1427+
.mem_enable_mask = BIT(4),
14091428
.mem_enable_ack_mask = BIT(4),
14101429
.branch = {
14111430
.halt_reg = 0x803c,
@@ -1429,6 +1448,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_1_clk = {
14291448
static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_2_clk = {
14301449
.mem_enable_reg = 0x840c,
14311450
.mem_ack_reg = 0x8420,
1451+
.mem_enable_mask = BIT(4),
14321452
.mem_enable_ack_mask = BIT(4),
14331453
.branch = {
14341454
.halt_reg = 0x8074,
@@ -1452,6 +1472,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_2_clk = {
14521472
static struct clk_mem_branch ecpri_cc_eth_100g_mac_c2c_hm_ref_clk = {
14531473
.mem_enable_reg = 0x8410,
14541474
.mem_ack_reg = 0x8424,
1475+
.mem_enable_mask = BIT(5),
14551476
.mem_enable_ack_mask = BIT(5),
14561477
.branch = {
14571478
.halt_reg = 0x80c4,
@@ -1475,6 +1496,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_mac_c2c_hm_ref_clk = {
14751496
static struct clk_mem_branch ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk = {
14761497
.mem_enable_reg = 0x8414,
14771498
.mem_ack_reg = 0x8428,
1499+
.mem_enable_mask = BIT(5),
14781500
.mem_enable_ack_mask = BIT(5),
14791501
.branch = {
14801502
.halt_reg = 0x80e8,
@@ -1498,6 +1520,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk = {
14981520
static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh0_hm_ref_clk = {
14991521
.mem_enable_reg = 0x8404,
15001522
.mem_ack_reg = 0x8418,
1523+
.mem_enable_mask = BIT(5),
15011524
.mem_enable_ack_mask = BIT(5),
15021525
.branch = {
15031526
.halt_reg = 0x802c,
@@ -1521,6 +1544,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh0_hm_ref_clk = {
15211544
static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh1_hm_ref_clk = {
15221545
.mem_enable_reg = 0x8408,
15231546
.mem_ack_reg = 0x841c,
1547+
.mem_enable_mask = BIT(5),
15241548
.mem_enable_ack_mask = BIT(5),
15251549
.branch = {
15261550
.halt_reg = 0x8064,
@@ -1544,6 +1568,7 @@ static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh1_hm_ref_clk = {
15441568
static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh2_hm_ref_clk = {
15451569
.mem_enable_reg = 0x840c,
15461570
.mem_ack_reg = 0x8420,
1571+
.mem_enable_mask = BIT(5),
15471572
.mem_enable_ack_mask = BIT(5),
15481573
.branch = {
15491574
.halt_reg = 0x809c,
@@ -1603,6 +1628,7 @@ static struct clk_branch ecpri_cc_eth_dbg_noc_axi_clk = {
16031628
static struct clk_mem_branch ecpri_cc_eth_phy_0_ock_sram_clk = {
16041629
.mem_enable_reg = 0x8404,
16051630
.mem_ack_reg = 0x8418,
1631+
.mem_enable_mask = BIT(6),
16061632
.mem_enable_ack_mask = BIT(6),
16071633
.branch = {
16081634
.halt_reg = 0xd140,
@@ -1621,6 +1647,7 @@ static struct clk_mem_branch ecpri_cc_eth_phy_0_ock_sram_clk = {
16211647
static struct clk_mem_branch ecpri_cc_eth_phy_1_ock_sram_clk = {
16221648
.mem_enable_reg = 0x8408,
16231649
.mem_ack_reg = 0x841C,
1650+
.mem_enable_mask = BIT(6),
16241651
.mem_enable_ack_mask = BIT(6),
16251652
.branch = {
16261653
.halt_reg = 0xd148,
@@ -1639,6 +1666,7 @@ static struct clk_mem_branch ecpri_cc_eth_phy_1_ock_sram_clk = {
16391666
static struct clk_mem_branch ecpri_cc_eth_phy_2_ock_sram_clk = {
16401667
.mem_enable_reg = 0x840c,
16411668
.mem_ack_reg = 0x8420,
1669+
.mem_enable_mask = BIT(6),
16421670
.mem_enable_ack_mask = BIT(6),
16431671
.branch = {
16441672
.halt_reg = 0xd150,
@@ -1657,6 +1685,7 @@ static struct clk_mem_branch ecpri_cc_eth_phy_2_ock_sram_clk = {
16571685
static struct clk_mem_branch ecpri_cc_eth_phy_3_ock_sram_clk = {
16581686
.mem_enable_reg = 0x8410,
16591687
.mem_ack_reg = 0x8424,
1688+
.mem_enable_mask = BIT(6),
16601689
.mem_enable_ack_mask = BIT(6),
16611690
.branch = {
16621691
.halt_reg = 0xd158,
@@ -1675,6 +1704,7 @@ static struct clk_mem_branch ecpri_cc_eth_phy_3_ock_sram_clk = {
16751704
static struct clk_mem_branch ecpri_cc_eth_phy_4_ock_sram_clk = {
16761705
.mem_enable_reg = 0x8414,
16771706
.mem_ack_reg = 0x8428,
1707+
.mem_enable_mask = BIT(6),
16781708
.mem_enable_ack_mask = BIT(6),
16791709
.branch = {
16801710
.halt_reg = 0xd160,

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