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Merge tag 'perf-tools-fixes-for-v6.19-2026-01-02' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools
Pull perf tool fixes and from Namhyung Kim: - skip building BPF skeletons if libopenssl is missing - a couple of test updates - handle error cases of filename__read_build_id() - support NVIDIA Olympus for ARM SPE profiling - update tool headers to sync with the kernel * tag 'perf-tools-fixes-for-v6.19-2026-01-02' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools: tools build: Fix the common set of features test wrt libopenssl tools headers: Sync syscall table with kernel sources tools headers: Sync linux/socket.h with kernel sources tools headers: Sync linux/gfp_types.h with kernel sources tools headers: Sync arm64 headers with kernel sources tools headers: Sync x86 headers with kernel sources tools headers: Sync UAPI sound/asound.h with kernel sources tools headers: Sync UAPI linux/mount.h with kernel sources tools headers: Sync UAPI linux/fs.h with kernel sources tools headers: Sync UAPI linux/fcntl.h with kernel sources tools headers: Sync UAPI KVM headers with kernel sources tools headers: Sync UAPI drm/drm.h with kernel sources perf arm-spe: Add NVIDIA Olympus to neoverse list tools headers arm64: Add NVIDIA Olympus part perf tests top: Make the test exclusive perf tests kvm: Avoid leaving perf.data.guest file around perf symbol: Fix ENOENT case for filename__read_build_id perf tools: Disable BPF skeleton if no libopenssl found tools/build: Add a feature test for libopenssl
2 parents bbbc721 + fe072f6 commit 805f9a0

35 files changed

Lines changed: 170 additions & 28 deletions

File tree

‎tools/arch/arm64/include/asm/cputype.h‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,6 @@
8181
#define ARM_CPU_PART_CORTEX_A78AE 0xD42
8282
#define ARM_CPU_PART_CORTEX_X1 0xD44
8383
#define ARM_CPU_PART_CORTEX_A510 0xD46
84-
#define ARM_CPU_PART_CORTEX_X1C 0xD4C
8584
#define ARM_CPU_PART_CORTEX_A520 0xD80
8685
#define ARM_CPU_PART_CORTEX_A710 0xD47
8786
#define ARM_CPU_PART_CORTEX_A715 0xD4D
@@ -93,6 +92,7 @@
9392
#define ARM_CPU_PART_NEOVERSE_V2 0xD4F
9493
#define ARM_CPU_PART_CORTEX_A720 0xD81
9594
#define ARM_CPU_PART_CORTEX_X4 0xD82
95+
#define ARM_CPU_PART_NEOVERSE_V3AE 0xD83
9696
#define ARM_CPU_PART_NEOVERSE_V3 0xD84
9797
#define ARM_CPU_PART_CORTEX_X925 0xD85
9898
#define ARM_CPU_PART_CORTEX_A725 0xD87
@@ -130,6 +130,7 @@
130130

131131
#define NVIDIA_CPU_PART_DENVER 0x003
132132
#define NVIDIA_CPU_PART_CARMEL 0x004
133+
#define NVIDIA_CPU_PART_OLYMPUS 0x010
133134

134135
#define FUJITSU_CPU_PART_A64FX 0x001
135136

@@ -171,7 +172,6 @@
171172
#define MIDR_CORTEX_A78AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE)
172173
#define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1)
173174
#define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)
174-
#define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C)
175175
#define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520)
176176
#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
177177
#define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715)
@@ -183,6 +183,7 @@
183183
#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
184184
#define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720)
185185
#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
186+
#define MIDR_NEOVERSE_V3AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3AE)
186187
#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
187188
#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
188189
#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
@@ -222,6 +223,7 @@
222223

223224
#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
224225
#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
226+
#define MIDR_NVIDIA_OLYMPUS MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_OLYMPUS)
225227
#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
226228
#define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
227229
#define MIDR_HISI_HIP09 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_HIP09)
@@ -245,7 +247,7 @@
245247
/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
246248
#define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
247249
#define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_CPU_VAR_REV(1, 0))
248-
#define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 | TCR_NFD0)
250+
#define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_EL1_NFD1 | TCR_EL1_NFD0)
249251

250252
#ifndef __ASSEMBLER__
251253

‎tools/arch/x86/include/asm/cpufeatures.h‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -314,6 +314,7 @@
314314
#define X86_FEATURE_SM4 (12*32+ 2) /* SM4 instructions */
315315
#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* "avx_vnni" AVX VNNI instructions */
316316
#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* "avx512_bf16" AVX512 BFLOAT16 instructions */
317+
#define X86_FEATURE_LASS (12*32+ 6) /* "lass" Linear Address Space Separation */
317318
#define X86_FEATURE_CMPCCXADD (12*32+ 7) /* CMPccXADD instructions */
318319
#define X86_FEATURE_ARCH_PERFMON_EXT (12*32+ 8) /* Intel Architectural PerfMon Extension */
319320
#define X86_FEATURE_FZRM (12*32+10) /* Fast zero-length REP MOVSB */
@@ -338,6 +339,7 @@
338339
#define X86_FEATURE_AMD_STIBP (13*32+15) /* Single Thread Indirect Branch Predictors */
339340
#define X86_FEATURE_AMD_STIBP_ALWAYS_ON (13*32+17) /* Single Thread Indirect Branch Predictors always-on preferred */
340341
#define X86_FEATURE_AMD_IBRS_SAME_MODE (13*32+19) /* Indirect Branch Restricted Speculation same mode protection*/
342+
#define X86_FEATURE_EFER_LMSLE_MBZ (13*32+20) /* EFER.LMSLE must be zero */
341343
#define X86_FEATURE_AMD_PPIN (13*32+23) /* "amd_ppin" Protected Processor Inventory Number */
342344
#define X86_FEATURE_AMD_SSBD (13*32+24) /* Speculative Store Bypass Disable */
343345
#define X86_FEATURE_VIRT_SSBD (13*32+25) /* "virt_ssbd" Virtualized Speculative Store Bypass Disable */
@@ -502,6 +504,15 @@
502504
#define X86_FEATURE_IBPB_EXIT_TO_USER (21*32+14) /* Use IBPB on exit-to-userspace, see VMSCAPE bug */
503505
#define X86_FEATURE_ABMC (21*32+15) /* Assignable Bandwidth Monitoring Counters */
504506
#define X86_FEATURE_MSR_IMM (21*32+16) /* MSR immediate form instructions */
507+
#define X86_FEATURE_SGX_EUPDATESVN (21*32+17) /* Support for ENCLS[EUPDATESVN] instruction */
508+
509+
#define X86_FEATURE_SDCIAE (21*32+18) /* L3 Smart Data Cache Injection Allocation Enforcement */
510+
#define X86_FEATURE_CLEAR_CPU_BUF_VM_MMIO (21*32+19) /*
511+
* Clear CPU buffers before VM-Enter if the vCPU
512+
* can access host MMIO (ignored for all intents
513+
* and purposes if CLEAR_CPU_BUF_VM is set).
514+
*/
515+
#define X86_FEATURE_X2AVIC_EXT (21*32+20) /* AMD SVM x2AVIC support for 4k vCPUs */
505516

506517
/*
507518
* BUG word(s)

‎tools/arch/x86/include/asm/msr-index.h‎

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -166,6 +166,10 @@
166166
* Processor MMIO stale data
167167
* vulnerabilities.
168168
*/
169+
#define ARCH_CAP_MCU_ENUM BIT(16) /*
170+
* Indicates the presence of microcode update
171+
* feature enumeration and status information.
172+
*/
169173
#define ARCH_CAP_FB_CLEAR BIT(17) /*
170174
* VERW clears CPU fill buffer
171175
* even on MDS_NO CPUs.
@@ -327,6 +331,26 @@
327331
PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \
328332
PERF_CAP_PEBS_TIMING_INFO)
329333

334+
/* Arch PEBS */
335+
#define MSR_IA32_PEBS_BASE 0x000003f4
336+
#define MSR_IA32_PEBS_INDEX 0x000003f5
337+
#define ARCH_PEBS_OFFSET_MASK 0x7fffff
338+
#define ARCH_PEBS_INDEX_WR_SHIFT 4
339+
340+
#define ARCH_PEBS_RELOAD 0xffffffff
341+
#define ARCH_PEBS_CNTR_ALLOW BIT_ULL(35)
342+
#define ARCH_PEBS_CNTR_GP BIT_ULL(36)
343+
#define ARCH_PEBS_CNTR_FIXED BIT_ULL(37)
344+
#define ARCH_PEBS_CNTR_METRICS BIT_ULL(38)
345+
#define ARCH_PEBS_LBR_SHIFT 40
346+
#define ARCH_PEBS_LBR (0x3ull << ARCH_PEBS_LBR_SHIFT)
347+
#define ARCH_PEBS_VECR_XMM BIT_ULL(49)
348+
#define ARCH_PEBS_GPR BIT_ULL(61)
349+
#define ARCH_PEBS_AUX BIT_ULL(62)
350+
#define ARCH_PEBS_EN BIT_ULL(63)
351+
#define ARCH_PEBS_CNTR_MASK (ARCH_PEBS_CNTR_GP | ARCH_PEBS_CNTR_FIXED | \
352+
ARCH_PEBS_CNTR_METRICS)
353+
330354
#define MSR_IA32_RTIT_CTL 0x00000570
331355
#define RTIT_CTL_TRACEEN BIT(0)
332356
#define RTIT_CTL_CYCLEACC BIT(1)
@@ -929,6 +953,10 @@
929953
#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
930954

931955
#define MSR_IA32_UCODE_WRITE 0x00000079
956+
957+
#define MSR_IA32_MCU_ENUMERATION 0x0000007b
958+
#define MCU_STAGING BIT(4)
959+
932960
#define MSR_IA32_UCODE_REV 0x0000008b
933961

934962
/* Intel SGX Launch Enclave Public Key Hash MSRs */
@@ -1226,6 +1254,8 @@
12261254
#define MSR_IA32_VMX_VMFUNC 0x00000491
12271255
#define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492
12281256

1257+
#define MSR_IA32_MCU_STAGING_MBOX_ADDR 0x000007a5
1258+
12291259
/* Resctrl MSRs: */
12301260
/* - Intel: */
12311261
#define MSR_IA32_L3_QOS_CFG 0xc81

‎tools/arch/x86/include/uapi/asm/kvm.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -502,6 +502,7 @@ struct kvm_sync_regs {
502502
/* vendor-specific groups and attributes for system fd */
503503
#define KVM_X86_GRP_SEV 1
504504
# define KVM_X86_SEV_VMSA_FEATURES 0
505+
# define KVM_X86_SNP_POLICY_BITS 1
505506

506507
struct kvm_vmx_nested_state_data {
507508
__u8 vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE];

‎tools/build/Makefile.feature‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -99,7 +99,8 @@ FEATURE_TESTS_BASIC := \
9999
libzstd \
100100
disassembler-four-args \
101101
disassembler-init-styled \
102-
file-handle
102+
file-handle \
103+
libopenssl
103104

104105
# FEATURE_TESTS_BASIC + FEATURE_TESTS_EXTRA is the complete list
105106
# of all feature tests
@@ -147,7 +148,8 @@ FEATURE_DISPLAY ?= \
147148
lzma \
148149
bpf \
149150
libaio \
150-
libzstd
151+
libzstd \
152+
libopenssl
151153

152154
#
153155
# Declare group members of a feature to display the logical OR of the detection

‎tools/build/feature/Makefile‎

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -67,12 +67,13 @@ FILES= \
6767
test-libopencsd.bin \
6868
test-clang.bin \
6969
test-llvm.bin \
70-
test-llvm-perf.bin \
70+
test-llvm-perf.bin \
7171
test-libaio.bin \
7272
test-libzstd.bin \
7373
test-clang-bpf-co-re.bin \
7474
test-file-handle.bin \
75-
test-libpfm4.bin
75+
test-libpfm4.bin \
76+
test-libopenssl.bin
7677

7778
FILES := $(addprefix $(OUTPUT),$(FILES))
7879

@@ -106,7 +107,7 @@ all: $(FILES)
106107
__BUILD = $(CC) $(CFLAGS) -MD -Wall -Werror -o $@ $(patsubst %.bin,%.c,$(@F)) $(LDFLAGS)
107108
BUILD = $(__BUILD) > $(@:.bin=.make.output) 2>&1
108109
BUILD_BFD = $(BUILD) -DPACKAGE='"perf"' -lbfd -ldl
109-
BUILD_ALL = $(BUILD) -fstack-protector-all -O2 -D_FORTIFY_SOURCE=2 -ldw -lelf -lnuma -lelf -lslang $(FLAGS_PERL_EMBED) $(FLAGS_PYTHON_EMBED) -ldl -lz -llzma -lzstd
110+
BUILD_ALL = $(BUILD) -fstack-protector-all -O2 -D_FORTIFY_SOURCE=2 -ldw -lelf -lnuma -lelf -lslang $(FLAGS_PERL_EMBED) $(FLAGS_PYTHON_EMBED) -ldl -lz -llzma -lzstd -lssl
110111

111112
__BUILDXX = $(CXX) $(CXXFLAGS) -MD -Wall -Werror -o $@ $(patsubst %.bin,%.cpp,$(@F)) $(LDFLAGS)
112113
BUILDXX = $(__BUILDXX) > $(@:.bin=.make.output) 2>&1
@@ -381,6 +382,9 @@ $(OUTPUT)test-file-handle.bin:
381382
$(OUTPUT)test-libpfm4.bin:
382383
$(BUILD) -lpfm
383384

385+
$(OUTPUT)test-libopenssl.bin:
386+
$(BUILD) -lssl
387+
384388
$(OUTPUT)test-bpftool-skeletons.bin:
385389
$(SYSTEM_BPFTOOL) version | grep '^features:.*skeletons' \
386390
> $(@:.bin=.make.output) 2>&1

‎tools/build/feature/test-all.c‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -142,6 +142,10 @@
142142
# include "test-libtraceevent.c"
143143
#undef main
144144

145+
#define main main_test_libopenssl
146+
# include "test-libopenssl.c"
147+
#undef main
148+
145149
int main(int argc, char *argv[])
146150
{
147151
main_test_libpython();
@@ -173,6 +177,7 @@ int main(int argc, char *argv[])
173177
main_test_reallocarray();
174178
main_test_libzstd();
175179
main_test_libtraceevent();
180+
main_test_libopenssl();
176181

177182
return 0;
178183
}

‎tools/build/feature/test-libopenssl.c‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,7 @@
1+
#include <openssl/ssl.h>
2+
#include <openssl/opensslv.h>
3+
4+
int main(void)
5+
{
6+
return SSL_library_init();
7+
}

‎tools/include/linux/gfp_types.h‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -55,9 +55,7 @@ enum {
5555
#ifdef CONFIG_LOCKDEP
5656
___GFP_NOLOCKDEP_BIT,
5757
#endif
58-
#ifdef CONFIG_SLAB_OBJ_EXT
5958
___GFP_NO_OBJ_EXT_BIT,
60-
#endif
6159
___GFP_LAST_BIT
6260
};
6361

@@ -98,11 +96,7 @@ enum {
9896
#else
9997
#define ___GFP_NOLOCKDEP 0
10098
#endif
101-
#ifdef CONFIG_SLAB_OBJ_EXT
10299
#define ___GFP_NO_OBJ_EXT BIT(___GFP_NO_OBJ_EXT_BIT)
103-
#else
104-
#define ___GFP_NO_OBJ_EXT 0
105-
#endif
106100

107101
/*
108102
* Physical address zone modifiers (see linux/mmzone.h - low four bits)

‎tools/include/uapi/asm-generic/unistd.h‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -857,9 +857,11 @@ __SYSCALL(__NR_open_tree_attr, sys_open_tree_attr)
857857
__SYSCALL(__NR_file_getattr, sys_file_getattr)
858858
#define __NR_file_setattr 469
859859
__SYSCALL(__NR_file_setattr, sys_file_setattr)
860+
#define __NR_listns 470
861+
__SYSCALL(__NR_listns, sys_listns)
860862

861863
#undef __NR_syscalls
862-
#define __NR_syscalls 470
864+
#define __NR_syscalls 471
863865

864866
/*
865867
* 32 bit systems traditionally used different

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