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| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/watchdog/renesas,rcar-gen3-wwdt.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: Renesas Window Watchdog Timer (WWDT) Controller |
| 8 | + |
| 9 | +maintainers: |
| 10 | + - Wolfram Sang <wsa+renesas@sang-engineering.com> |
| 11 | + |
| 12 | +properties: |
| 13 | + compatible: |
| 14 | + oneOf: |
| 15 | + - items: |
| 16 | + - enum: |
| 17 | + - renesas,r8a77970-wwdt # R-Car V3M |
| 18 | + - renesas,r8a77980-wwdt # R-Car V3H |
| 19 | + - const: renesas,rcar-gen3-wwdt |
| 20 | + |
| 21 | + - items: |
| 22 | + - enum: |
| 23 | + - renesas,r8a779a0-wwdt # R-Car V3U |
| 24 | + - renesas,r8a779f0-wwdt # R-Car S4 |
| 25 | + - renesas,r8a779g0-wwdt # R-Car V4H |
| 26 | + - renesas,r8a779h0-wwdt # R-Car V4M |
| 27 | + - const: renesas,rcar-gen4-wwdt |
| 28 | + |
| 29 | + reg: |
| 30 | + maxItems: 1 |
| 31 | + |
| 32 | + interrupts: |
| 33 | + items: |
| 34 | + - description: Pretimeout, 75% of overflow reached |
| 35 | + - description: Error occurred |
| 36 | + |
| 37 | + interrupt-names: |
| 38 | + items: |
| 39 | + - const: pretimeout |
| 40 | + - const: error |
| 41 | + |
| 42 | + clocks: |
| 43 | + items: |
| 44 | + - description: Counting clock |
| 45 | + - description: Bus clock |
| 46 | + |
| 47 | + clock-names: |
| 48 | + items: |
| 49 | + - const: cnt |
| 50 | + - const: bus |
| 51 | + |
| 52 | + resets: |
| 53 | + minItems: 1 |
| 54 | + maxItems: 2 |
| 55 | + |
| 56 | + reset-names: |
| 57 | + minItems: 1 |
| 58 | + items: |
| 59 | + - const: cnt |
| 60 | + - const: bus |
| 61 | + |
| 62 | + power-domains: |
| 63 | + maxItems: 1 |
| 64 | + |
| 65 | +required: |
| 66 | + - compatible |
| 67 | + - reg |
| 68 | + - interrupts |
| 69 | + - interrupt-names |
| 70 | + - clocks |
| 71 | + - clock-names |
| 72 | + - resets |
| 73 | + - reset-names |
| 74 | + - power-domains |
| 75 | + |
| 76 | +allOf: |
| 77 | + - $ref: watchdog.yaml# |
| 78 | + |
| 79 | + - if: |
| 80 | + properties: |
| 81 | + compatible: |
| 82 | + contains: |
| 83 | + enum: |
| 84 | + - renesas,r8a779a0-wwdt |
| 85 | + - renesas,r8a779f0-wwdt |
| 86 | + then: |
| 87 | + properties: |
| 88 | + resets: |
| 89 | + minItems: 2 |
| 90 | + reset-names: |
| 91 | + minItems: 2 |
| 92 | + |
| 93 | +additionalProperties: false |
| 94 | + |
| 95 | +examples: |
| 96 | + - | |
| 97 | + #include <dt-bindings/clock/r8a779g0-cpg-mssr.h> |
| 98 | + #include <dt-bindings/power/r8a779g0-sysc.h> |
| 99 | + #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 100 | +
|
| 101 | + watchdog@ffc90000 { |
| 102 | + compatible = "renesas,r8a779g0-wwdt", |
| 103 | + "renesas,rcar-gen4-wwdt"; |
| 104 | + reg = <0xffc90000 0x10>; |
| 105 | + interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, |
| 106 | + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; |
| 107 | + interrupt-names = "pretimeout", "error"; |
| 108 | + clocks = <&cpg CPG_CORE R8A779G0_CLK_R>, |
| 109 | + <&cpg CPG_CORE R8A779G0_CLK_SASYNCRT>; |
| 110 | + clock-names = "cnt", "bus"; |
| 111 | + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; |
| 112 | + resets = <&cpg 1200>; |
| 113 | + reset-names = "cnt"; |
| 114 | + }; |
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