ram: changes to ram.tcl and generate ram example

Signed-off-by: braydenl9988 <braydenl9988@gmail.com>

Author: braydenlouie

src/ram/src/ram.tcl

@@ -48,3 +48,123 @@ proc generate_ram_netlist { args } {
   ram::generate_ram_netlist_cmd $bytes_per_word $word_count $storage_cell \
     $tristate_cell $inv_cell $read_ports
 }
+
+sta::define_cmd_args "generate_ram" {-bytes_per_word bits
+                                     -word_count words
+				     [-storage_cell name]
+                                     [-tristate_cell name]
+                                     [-inv_cell name]
+                                     [-read_ports count]
+				     -power_net name
+			             -ground_net name
+				     -routing_layer config
+				     -ver_layer config
+				     -hor_layer config
+				     -filler_cells fillers}
+# user arguments for generate ram netlist arguments
+proc generate_ram { args } {
+  sta::parse_key_args "generate_ram" args \
+    keys {-bytes_per_word -word_count -storage_cell -tristate_cell -inv_cell -read_ports
+      -power_net -ground_net -routing_layer -ver_layer -hor_layer -filler_cells} flags {}
+
+  generate_ram_netlist \
+    -bytes_per_word $keys(-bytes_per_word) \
+    -word_count $keys(-word_count) \
+    -storage_cell $keys(-storage_cell) \
+    -read_ports $keys(-read_ports)
+
+  ord::design_created
+
+  if { [info exists keys(-power_net)] } {
+    set power_net $keys(-power_net)
+  } else {
+    utl::error RAM 5 "The -power_net argument must be specified."
+  }
+
+  if { [info exists keys(-ground_net)] } {
+    set ground_net $keys(-ground_net)
+  } else {
+    utl::error RAM 6 "The -ground_net argument must be specified."
+  }
+
+  if { [info exists keys(-routing_layer)] } {
+    set routing_layer $keys(-routing_layer)
+  } else {
+    utl::error RAM 9 "The -routing_layer argument must be specified."
+  }
+
+  if { [llength $routing_layer] != 2 } {
+    utl::error RAM 12 "-routing_layer is not a list of 2 values"
+  } else {
+    lassign $routing_layer route_name route_width
+  }
+
+  if { [info exists keys(-ver_layer)] } {
+    set ver_layer $keys(-ver_layer)
+  } else {
+    utl::error RAM 13 "The -ver_layer argument must be specified."
+  }
+
+  if { [llength $ver_layer] != 3 } {
+    utl::error RAM 14 "-ver_layer is not a list of 2 values"
+  } else {
+    lassign $ver_layer ver_name ver_width ver_pitch
+  }
+
+  if { [info exists keys(-hor_layer)] } {
+    set hor_layer $keys(-hor_layer)
+  } else {
+    utl::error RAM 15 "The -hor_layer argument must be specified."
+  }
+
+  if { [llength $hor_layer] != 3 } {
+    utl::error RAM 17 "-hor_layer is not a list of 2 values"
+  } else {
+    lassign $hor_layer hor_name hor_width hor_pitch
+  }
+
+  if { [info exists keys(-filler_cells)] } {
+    set filler_cells $keys(-filler_cells)
+  } else {
+    utl::error RAM 18 "The -filler_cells argument must be specified."
+  }
+
+  add_global_connection -net VDD -pin_pattern $power_net -power
+  add_global_connection -net VSS -pin_pattern $ground_net -ground
+
+  global_connect
+
+  set_voltage_domain -power VDD -ground VSS
+  define_pdn_grid -name ram_grid -voltage_domains {CORE}
+
+  add_pdn_stripe -grid ram_grid -layer $route_name \
+    -width $route_width -followpins -extend_to_boundary
+  add_pdn_stripe -grid ram_grid -layer $ver_name \
+    -width $ver_width -pitch $ver_pitch -extend_to_boundary
+  add_pdn_stripe -grid ram_grid -layer $hor_name \
+    -width $hor_width -pitch $hor_pitch -extend_to_boundary
+
+  add_pdn_connect -layers [list $route_name $ver_name]
+  add_pdn_connect -layers [list $ver_name $hor_name]
+
+  pdngen
+
+  make_tracks -x_offset 0 -y_offset 0
+  set_io_pin_constraint -direction output -region top:*
+  set_io_pin_constraint -pin_names {D[*]} -region top:*
+
+  place_pins -hor_layers $hor_name -ver_layers $ver_name
+
+  filler_placement $filler_cells
+
+  global_route
+  detailed_route
+
+  set lef_file [make_result_file make_8x8.lef]
+  write_abstract_lef $lef_file
+  diff_files make_8x8.lefok $lef_file
+
+  set def_file [make_result_file make_8x8.def]
+  write_def $def_file
+  diff_files make_8x8.defok $def_file
+}

src/ram/test/make_8x8.tcl

@@ -1,50 +1,21 @@
 source "helpers.tcl"
 
-set_thread_count [expr [cpu_count] / 4]
+set_thread_count {[expr [cpu_count] / 4]}
 
 read_liberty sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib
 
 read_lef sky130hd/sky130hd.tlef
 read_lef sky130hd/sky130_fd_sc_hd_merged.lef
 
-generate_ram_netlist \
+generate_ram \
   -bytes_per_word 1 \
   -word_count 8 \
   -read_ports 2 \
-  -storage_cell sky130_fd_sc_hd__dlxtp_1
-#    -tristate_cell sky130_fd_sc_hd__ebufn_2
-#    -inv_cell sky130_fd_sc_hd__inv_1
-
-ord::design_created
-
-add_global_connection -net VDD -pin_pattern {^VPWR$} -power
-add_global_connection -net VSS -pin_pattern {^VGND$} -ground
-global_connect
-set_voltage_domain -power VDD -ground VSS
-define_pdn_grid -name ram_grid -voltage_domains {CORE}
-add_pdn_stripe -grid ram_grid -layer met1 -followpins -width 0.48
-add_pdn_stripe -grid ram_grid -layer met2 -width 0.48 -pitch 40 -extend_to_boundary
-add_pdn_stripe -grid ram_grid -layer met3 -width 0.48 -pitch 20 -extend_to_boundary
-add_pdn_connect -layers {met1 met2}
-add_pdn_connect -layers {met2 met3}
-
-pdngen
-
-make_tracks -x_offset 0 -y_offset 0
-set_io_pin_constraint -direction output -region top:*
-set_io_pin_constraint -pin_names {D[*]} -region top:*
-place_pins -hor_layers met3 -ver_layers met2
-
-filler_placement {sky130_fd_sc_hd__fill_1 sky130_fd_sc_hd__fill_2 \
-	sky130_fd_sc_hd__fill_4 sky130_fd_sc_hd__fill_8}
-
-global_route
-detailed_route -verbose 0
-
-set lef_file [make_result_file make_8x8.lef]
-write_abstract_lef $lef_file
-diff_files make_8x8.lefok $lef_file
-
-set def_file [make_result_file make_8x8.def]
-write_def $def_file
-diff_files make_8x8.defok $def_file
+  -storage_cell sky130_fd_sc_hd__dlxtp_1 \
+  -power_net VPWR \
+  -ground_net VGND \
+  -routing_layer {met1 0.48} \
+  -ver_layer {met2 0.48 40} \
+  -hor_layer {met3 0.48 20} \
+  -filler_cells {sky130_fd_sc_hd__fill_1 sky130_fd_sc_hd__fill_2 \
+	  sky130_fd_sc_hd__fill_4 sky130_fd_sc_hd__fill_8}