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Added a new class tst::IntegratedFixture
- Integrated multiple modules including EST and RSZ. - Contains readVerilogAndSetup() to read a test design from a verilog easily. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
1 parent 6faa972 commit 32deade

8 files changed

Lines changed: 259 additions & 342 deletions

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‎src/dbSta/test/BUILD‎

Lines changed: 1 addition & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -211,18 +211,11 @@ cc_test(
211211
"cpp/TestDbSta_0.v",
212212
],
213213
deps = [
214-
"//src/ant",
215214
"//src/dbSta",
216215
"//src/dbSta:dbNetwork",
217-
"//src/dbSta:dbReadVerilog",
218-
"//src/dpl",
219-
"//src/est",
220-
"//src/grt",
221216
"//src/odb",
222-
"//src/rsz",
223217
"//src/sta:opensta_lib",
224-
"//src/stt",
225-
"//src/tst",
218+
"//src/tst:integrated_fixture",
226219
"//src/utl",
227220
"@googletest//:gtest",
228221
"@googletest//:gtest_main",

‎src/dbSta/test/cpp/TestDbSta.cc‎

Lines changed: 4 additions & 166 deletions
Original file line numberDiff line numberDiff line change
@@ -3,186 +3,24 @@
33

44
#include <cassert>
55
#include <cstdio>
6-
#include <fstream>
7-
#include <memory>
86
#include <string>
97

10-
#include "ant/AntennaChecker.hh"
11-
#include "db_sta/dbNetwork.hh"
12-
#include "db_sta/dbReadVerilog.hh"
13-
#include "db_sta/dbSta.hh"
14-
#include "dpl/Opendp.h"
15-
#include "est/EstimateParasitics.h"
16-
#include "grt/GlobalRouter.h"
178
#include "gtest/gtest.h"
189
#include "odb/db.h"
19-
#include "odb/dbTypes.h"
20-
#include "rsz/Resizer.hh"
21-
#include "sta/Clock.hh"
22-
#include "sta/Graph.hh"
23-
#include "sta/NetworkClass.hh"
24-
#include "sta/Sdc.hh"
25-
#include "sta/SdcClass.hh"
26-
#include "sta/Sta.hh"
27-
#include "sta/Units.hh"
28-
#include "sta/VerilogWriter.hh"
29-
#include "stt/SteinerTreeBuilder.h"
30-
#include "tst/fixture.h"
31-
#include "utl/CallBackHandler.h"
32-
#include "utl/Logger.h"
10+
#include "tst/IntegratedFixture.h"
3311

3412
namespace rsz {
3513

36-
class TestDbSta : public tst::Fixture
14+
class TestDbSta : public tst::IntegratedFixture
3715
{
3816
protected:
39-
void readVerilogAndSetup(const std::string& verilog_file);
40-
void dumpVerilogAndOdb(const std::string& name) const;
41-
4217
TestDbSta()
43-
: stt_(db_.get(), &logger_),
44-
callback_handler_(&logger_),
45-
dp_(db_.get(), &logger_),
46-
ant_(db_.get(), &logger_),
47-
grt_(&logger_,
48-
&callback_handler_,
49-
&stt_,
50-
db_.get(),
51-
sta_.get(),
52-
&ant_,
53-
&dp_),
54-
ep_(&logger_, &callback_handler_, db_.get(), sta_.get(), &stt_, &grt_),
55-
resizer_(&logger_, db_.get(), sta_.get(), &stt_, &grt_, &dp_, &ep_)
18+
: tst::IntegratedFixture(tst::IntegratedFixture::Technology::Nangate45,
19+
"_main/src/dbSta/test/")
5620
{
57-
readLiberty(getFilePath(prefix_ + "Nangate45/Nangate45_typ.lib"));
58-
lib_ = loadTechAndLib("Nangate45",
59-
"Nangate45",
60-
getFilePath(prefix_ + "Nangate45/Nangate45.lef"));
61-
62-
db_->setLogger(&logger_);
63-
db_network_ = sta_->getDbNetwork();
64-
db_network_->setHierarchy();
65-
66-
if (debug_) {
67-
logger_.setDebugLevel(utl::ODB, "DB_ECO", 3);
68-
}
6921
}
70-
71-
odb::dbLib* lib_;
72-
odb::dbBlock* block_;
73-
sta::dbNetwork* db_network_;
74-
75-
stt::SteinerTreeBuilder stt_;
76-
utl::CallBackHandler callback_handler_;
77-
dpl::Opendp dp_;
78-
ant::AntennaChecker ant_;
79-
grt::GlobalRouter grt_;
80-
est::EstimateParasitics ep_;
81-
rsz::Resizer resizer_;
82-
bool debug_ = false; // Set to true to generate debug output
83-
84-
const std::string prefix_ = "_main/src/dbSta/test/";
8522
};
8623

87-
void TestDbSta::readVerilogAndSetup(const std::string& verilog_file)
88-
{
89-
ord::dbVerilogNetwork verilog_network(sta_.get());
90-
sta::VerilogReader verilog_reader(&verilog_network);
91-
verilog_reader.read(getFilePath(prefix_ + "cpp/" + verilog_file).c_str());
92-
93-
ord::dbLinkDesign(
94-
"top", &verilog_network, db_.get(), &logger_, true /*hierarchy = */);
95-
96-
sta_->postReadDb(db_.get());
97-
98-
block_ = db_->getChip()->getBlock();
99-
block_->setDefUnits(lib_->getTech()->getLefUnits());
100-
block_->setDieArea(odb::Rect(0, 0, 1000, 1000));
101-
sta_->postReadDef(block_);
102-
103-
// Timing setup
104-
sta::Cell* top_cell = db_network_->cell(db_network_->topInstance());
105-
sta::Port* clk_port = db_network_->findPort(top_cell, "clk");
106-
sta::Pin* clk_pin
107-
= db_network_->findPin(db_network_->topInstance(), clk_port);
108-
109-
sta::PinSet* pinset = new sta::PinSet(db_network_);
110-
pinset->insert(clk_pin);
111-
sta::PinSet* clk_pins = new sta::PinSet;
112-
clk_pins->insert(db_network_->dbToSta(block_->findBTerm("clk")));
113-
114-
// 0.5ns
115-
double period = sta_->units()->timeUnit()->userToSta(0.5);
116-
sta::FloatSeq* waveform = new sta::FloatSeq;
117-
waveform->push_back(0);
118-
waveform->push_back(period / 2.0);
119-
120-
sta_->makeClock("clk",
121-
pinset,
122-
/*add_to_pins=*/false,
123-
/*period=*/period,
124-
waveform,
125-
/*comment=*/nullptr);
126-
127-
sta::Sdc* sdc = sta_->sdc();
128-
const sta::RiseFallBoth* rf = sta::RiseFallBoth::riseFall();
129-
sta::Clock* clk = sdc->findClock("clk");
130-
const sta::RiseFall* clk_rf = sta::RiseFall::rise();
131-
132-
for (odb::dbBTerm* term : block_->getBTerms()) {
133-
sta::Pin* pin = db_network_->dbToSta(term);
134-
if (pin == nullptr) {
135-
continue;
136-
}
137-
if (sdc->isClock(pin)) {
138-
continue;
139-
}
140-
141-
odb::dbIoType io_type = term->getIoType();
142-
if (io_type == odb::dbIoType::INPUT) {
143-
sta_->setInputDelay(pin,
144-
rf,
145-
clk,
146-
clk_rf,
147-
nullptr,
148-
false,
149-
false,
150-
sta::MinMaxAll::all(),
151-
true,
152-
0.0);
153-
} else if (io_type == odb::dbIoType::OUTPUT) {
154-
sta_->setOutputDelay(pin,
155-
rf,
156-
clk,
157-
clk_rf,
158-
nullptr,
159-
false,
160-
false,
161-
sta::MinMaxAll::all(),
162-
true,
163-
0.0);
164-
}
165-
}
166-
167-
sta_->ensureGraph();
168-
sta_->ensureLevelized();
169-
170-
resizer_.initBlock();
171-
ep_.estimateWireParasitics();
172-
}
173-
174-
void TestDbSta::dumpVerilogAndOdb(const std::string& name) const
175-
{
176-
// Write verilog
177-
std::string vlog_file = name + ".v";
178-
sta::writeVerilog(vlog_file.c_str(), true, false, {}, sta_->network());
179-
180-
// Dump ODB content
181-
std::ofstream orig_odb_file(name + "_odb.txt");
182-
block_->debugPrintContent(orig_odb_file);
183-
orig_odb_file.close();
184-
}
185-
18624
TEST_F(TestDbSta, TestIsConnected)
18725
{
18826
std::string test_name = "TestDbSta_0";

‎src/rsz/test/BUILD‎

Lines changed: 1 addition & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -324,18 +324,11 @@ cc_test(
324324
"cpp/TestBufferRemoval3_6.v",
325325
],
326326
deps = [
327-
"//src/ant",
328327
"//src/dbSta",
329328
"//src/dbSta:dbNetwork",
330-
"//src/dbSta:dbReadVerilog",
331-
"//src/dpl",
332-
"//src/est",
333-
"//src/grt",
334329
"//src/odb",
335-
"//src/rsz",
336330
"//src/sta:opensta_lib",
337-
"//src/stt",
338-
"//src/tst",
331+
"//src/tst:integrated_fixture",
339332
"//src/utl",
340333
"@googletest//:gtest",
341334
"@googletest//:gtest_main",

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