Skip to content

Commit 38879d4

Browse files
mguthausmguthaus
committed
Add gcd_asap7 as initial asap7 regression test in OR.
Signed-off-by: Matthew Guthaus <mrg@ucsc.edu>
1 parent b7399ed commit 38879d4

9 files changed

Lines changed: 6730 additions & 0 deletions

File tree

‎test/BUILD‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -93,6 +93,7 @@ BIG_TESTS = [
9393
"gcd_sky130hd_fast_slow",
9494
"gcd_sky130hd",
9595
"gcd_sky130hs",
96+
"gcd_asap7",
9697
"ibex_sky130hd",
9798
"ibex_sky130hs",
9899
"jpeg_sky130hd",

‎test/asap7/asap7.pdn.tcl‎

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
# macro level counterpart to BLOCKS_grid_strategy.tcl
2+
3+
####################################
4+
# global connections
5+
####################################
6+
add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power
7+
add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground
8+
9+
####################################
10+
# voltage domains
11+
####################################
12+
set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
13+
14+
####################################
15+
# standard cell grid
16+
# M1 M2 are for follow pin, width derived from PG rail in standard cell
17+
# M5 stripe width rerived from one of width allowed in LEF, offset and pitch
18+
# put stripe on M5 track
19+
# M4 M5 ring follow stripe width
20+
####################################
21+
define_pdn_grid -name {top} -voltage_domains {CORE} -pins {M5}
22+
23+
add_pdn_ring -grid {top} -layers {M5 M4} -widths {0.12 0.12} -spacings {0.072} -core_offset {0.084}
24+
25+
add_pdn_stripe -grid {top} -layer {M1} -width {0.018} -pitch {0.54} -offset {0} -followpins
26+
add_pdn_stripe -grid {top} -layer {M2} -width {0.018} -pitch {0.54} -offset {0} -followpins
27+
28+
add_pdn_stripe -grid {top} -layer {M5} -width {0.12} -spacing {0.072} -pitch {2.976} -offset {1.5} \
29+
-extend_to_core_ring
30+
31+
add_pdn_connect -grid {top} -layers {M1 M2}
32+
add_pdn_connect -grid {top} -layers {M2 M5}
33+
add_pdn_connect -grid {top} -layers {M4 M5}

‎test/asap7/asap7.tracks.tcl‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
make_tracks Pad -x_offset 0.116 -x_pitch 0.080 -y_offset 0.116 -y_pitch 0.080
2+
make_tracks M9 -x_offset 0.116 -x_pitch 0.080 -y_offset 0.116 -y_pitch 0.080
3+
make_tracks M8 -x_offset 0.116 -x_pitch 0.080 -y_offset 0.116 -y_pitch 0.080
4+
make_tracks M7 -x_offset 0.016 -x_pitch 0.064 -y_offset 0.016 -y_pitch 0.064
5+
make_tracks M6 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.016 -y_pitch 0.064
6+
make_tracks M5 -x_offset 0.012 -x_pitch 0.048 -y_offset 0.012 -y_pitch 0.048
7+
make_tracks M4 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.012 -y_pitch 0.048
8+
make_tracks M3 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036
9+
10+
make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.045 -y_pitch 0.270
11+
make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.081 -y_pitch 0.270
12+
make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.117 -y_pitch 0.270
13+
make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.153 -y_pitch 0.270
14+
make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.189 -y_pitch 0.270
15+
make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.225 -y_pitch 0.270
16+
make_tracks M2 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.270 -y_pitch 0.270
17+
18+
make_tracks M1 -x_offset 0.009 -x_pitch 0.036 -y_offset 0.009 -y_pitch 0.036

‎test/asap7/asap7.vars‎

Lines changed: 53 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,53 @@
1+
set platform "asap7"
2+
set tech_lef "asap7/asap7_tech_1x_201209.lef"
3+
set std_cell_lef "asap7/asap7sc7p5t_28_L_1x_220121a.lef"
4+
set extra_lef {"asap7/asap7sc7p5t_28_R_1x_220121a.lef" "asap7/asap7sc7p5t_28_SL_1x_220121a.lef"}
5+
set liberty_file "asap7/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz"
6+
set extra_liberty {"asap7/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz" "asap7/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz" "asap7/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz" "asap7/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib"}
7+
set site "asap7sc7p5t"
8+
set pdn_cfg "asap7/asap7.pdn.tcl"
9+
set tracks_file "asap7/asap7.tracks.tcl"
10+
set io_placer_hor_layer M4
11+
set io_placer_ver_layer M5
12+
set tapcell_args "-distance 25 \
13+
-tapcell_master TAPCELL_ASAP7_75t_R \
14+
-endcap_master TAPCELL_ASAP7_75t_R"
15+
set global_place_density 0.3
16+
# default value
17+
set global_place_density_penalty 8e-5
18+
# placement padding in SITE widths applied to both sides
19+
set global_place_pad 2
20+
set detail_place_pad 1
21+
22+
set pre_placed_macros_file ""
23+
set macro_place_halo {10 10}
24+
25+
set layer_rc_file "asap7/setRC.tcl"
26+
set wire_rc_layer "M3"
27+
set wire_rc_layer_clk "M6"
28+
set tielo_port "TIELOx1_ASAP7_75t_R/L"
29+
set tiehi_port "TIEHIx1_ASAP7_75t_R/H"
30+
set dont_use {*x1p*_ASAP7* *xp*_ASAP7* SDF* ICG*}
31+
# tie hi/low instance to load separation (microns)
32+
set tie_separation 5
33+
set cts_buffer "BUFx4_ASAP7_75t_R"
34+
set cts_cluster_diameter 50
35+
set filler_cells "FILLER*"
36+
37+
# global route
38+
set global_routing_layers M2-M6
39+
set global_routing_clock_layers M4-M6
40+
set global_routing_layer_adjustments {{{M2-M7} 0.25}}
41+
42+
# detail route
43+
set min_routing_layer M2
44+
set max_routing_layer M6
45+
46+
set rcx_rules_file "asap7/rcx_patterns.rules"
47+
48+
# To remove [WARNING STA-1212] from the logs for ASAP7.
49+
# /OpenROAD-flow-scripts/flow/platforms/asap7/lib/asap7sc7p5t_SIMPLE_RVT_TT_nldm_211120.lib.gz
50+
# line 13178, timing group from output port.
51+
# Added following suppress_message
52+
suppress_message STA 1212
53+

0 commit comments

Comments
 (0)