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malibertymaliberty
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Merge pull request #7902 from The-OpenROAD-Project-staging/secure-jhkim-hier-fix
Secure jhkim hier fix
2 parents abdaff9 + 77aaaa3 commit 5ce2d11

26 files changed

Lines changed: 9160 additions & 4 deletions

‎src/rsz/src/Rebuffer.cc‎

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1815,16 +1815,22 @@ int Rebuffer::exportBufferTree(const BufferedNetPtr& choice,
18151815
Instance* parent = parent_in;
18161816
switch (choice->type()) {
18171817
case BufferedNetType::buffer: {
1818-
std::string buffer_name
1819-
= resizer_->makeUniqueInstName(instance_base_name);
1818+
// Decide new buffer name
1819+
std::string buffer_full_name;
1820+
if (parent && parent != db_network_->topInstance()) {
1821+
buffer_full_name = db_network_->pathName(parent);
1822+
buffer_full_name += db_network_->pathDivider();
1823+
}
1824+
buffer_full_name += instance_base_name;
1825+
buffer_full_name = resizer_->makeUniqueInstName(buffer_full_name.c_str());
18201826

18211827
// HFix: make net in hierarchy
18221828
std::string net_name = resizer_->makeUniqueNetName();
18231829
Net* net2 = db_network_->makeNet(net_name.c_str(), parent);
18241830

18251831
LibertyCell* buffer_cell = choice->bufferCell();
18261832
Instance* buffer = resizer_->makeBuffer(
1827-
buffer_cell, buffer_name.c_str(), parent, choice->location());
1833+
buffer_cell, buffer_full_name.c_str(), parent, choice->location());
18281834

18291835
resizer_->level_drvr_vertices_valid_ = false;
18301836
LibertyPort *input, *output;
@@ -1837,7 +1843,7 @@ int Rebuffer::exportBufferTree(const BufferedNetPtr& choice,
18371843
"",
18381844
level,
18391845
sdc_network_->pathName(net),
1840-
buffer_name.c_str(),
1846+
buffer_full_name.c_str(),
18411847
buffer_cell->name(),
18421848
sdc_network_->pathName(net2));
18431849

‎src/rsz/test/CMakeLists.txt‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -89,6 +89,8 @@ or_integration_tests(
8989
repair_setup7
9090
repair_setup7_limit
9191
repair_setup8
92+
repair_setup9
93+
repair_setup9_hier
9294
repair_setup_undo
9395
repair_slew1
9496
repair_slew2
@@ -147,6 +149,8 @@ or_integration_tests(
147149
resize_slack1
148150
resize_slack2
149151
resize_slack3
152+
rebuffer1
153+
rebuffer1_hier
150154
set_dont_touch1
151155
set_dont_use1
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split_load_hier

‎src/rsz/test/rebuffer1.def‎

Lines changed: 944 additions & 0 deletions
Large diffs are not rendered by default.

‎src/rsz/test/rebuffer1.ok‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,16 @@
1+
[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
2+
[INFO ODB-0128] Design: top
3+
[INFO ODB-0252] Updated 7 pins.
4+
[INFO ODB-0253] Updated 34 components.
5+
[INFO ODB-0254] Updated 29 nets and 81 connections.
6+
worst slack max -0.43
7+
worst slack min -0.05
8+
tns max -3.964
9+
Iter | Area | Removed | Inserted | Pins
10+
| | Buffers | Buffers | Remaining
11+
-------------------------------------------------------
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0 | +0.0% | 0 | 0 | 1
13+
final | +1.7% | 0 | 1 | 0
14+
-------------------------------------------------------
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No differences found.
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No differences found.

‎src/rsz/test/rebuffer1.tcl‎

Lines changed: 44 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,44 @@
1+
# rebuffering test in flattened flow
2+
source "helpers.tcl"
3+
4+
define_corners fast slow
5+
read_liberty -corner slow Nangate45/Nangate45_slow.lib
6+
read_liberty -corner fast Nangate45/Nangate45_fast.lib
7+
read_lef Nangate45/Nangate45.lef
8+
read_verilog rebuffer1.v
9+
link_design top
10+
read_def -floorplan_initialize rebuffer1.def
11+
12+
#place the design
13+
#initialize_floorplan -die_area "0 0 40 1200" -core_area "0 0 40 1200" \
14+
# -site FreePDK45_38x28_10R_NP_162NW_34O
15+
#global_placement -skip_nesterov_place
16+
#detailed_placement
17+
18+
#sdc
19+
create_clock -period 0.3 clk
20+
set_clock_uncertainty -hold 0.1 [get_clocks clk]
21+
22+
#parasitic
23+
source Nangate45/Nangate45.rc
24+
set_wire_rc -layer metal3
25+
estimate_parasitics -placement
26+
27+
report_worst_slack -max
28+
report_worst_slack -min
29+
report_tns -digits 3
30+
31+
#set_debug_level RSZ rebuffer 10
32+
33+
rsz::fully_rebuffer [get_pins u_mid1/u_leaf2/dff2/Q]
34+
35+
# generate .v and .def files
36+
set verilog_filename "rebuffer1_out.v"
37+
set rebuffered_verilog_filename [make_result_file $verilog_filename]
38+
write_verilog $rebuffered_verilog_filename
39+
diff_file ${verilog_filename}ok $rebuffered_verilog_filename
40+
41+
set def_filename "rebuffer1_out.def"
42+
set rebuffered_def_filename [make_result_file $def_filename]
43+
write_def $rebuffered_def_filename
44+
diff_file ${def_filename}ok $rebuffered_def_filename

‎src/rsz/test/rebuffer1.v‎

Lines changed: 170 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,170 @@
1+
// Defines a leaf-level module with a simple register-to-register path
2+
// including a buffer chain. This creates a straightforward sequential path.
3+
module leaf1 (
4+
input clk,
5+
input in1,
6+
output out1
7+
);
8+
9+
wire n1, n2, n3;
10+
DFF_X1 dff1 (.D(in1), .CK(clk), .Q(n1));
11+
BUF_X1 buf1 (.A(n1), .Z(n2));
12+
BUF_X1 buf2 (.A(n2), .Z(n3));
13+
DFF_X1 dff2 (.D(n3), .CK(clk), .Q(out1));
14+
15+
endmodule
16+
17+
// Defines a leaf-level module with fanout, where one signal drives
18+
// multiple buffers and registers. This introduces path divergence.
19+
module leaf2 (
20+
input clk,
21+
input in1,
22+
output out1,
23+
output out2
24+
);
25+
26+
wire n1, n2, n3;
27+
DFF_X1 dff1 (.D(in1), .CK(clk), .Q(n1));
28+
BUF_X1 buf1 (.A(n1), .Z(n2));
29+
BUF_X1 buf2 (.A(n1), .Z(n3));
30+
DFF_X1 dff2 (.D(n2), .CK(clk), .Q(out1));
31+
DFF_X1 dff3 (.D(n3), .CK(clk), .Q(out2));
32+
33+
endmodule
34+
35+
// Defines a leaf-level module with a longer buffer chain to create
36+
// a path with more significant delay.
37+
module leaf3 (
38+
input clk,
39+
input in1,
40+
output out1
41+
);
42+
43+
wire n1, n2, n3, n4, n5;
44+
DFF_X1 dff1 (.D(in1), .CK(clk), .Q(n1));
45+
BUF_X1 buf1 (.A(n1), .Z(n2));
46+
BUF_X1 buf2 (.A(n2), .Z(n3));
47+
BUF_X1 buf3 (.A(n3), .Z(n4));
48+
BUF_X1 buf4 (.A(n4), .Z(n5));
49+
DFF_X1 dff2 (.D(n5), .CK(clk), .Q(out1));
50+
51+
endmodule
52+
53+
// Defines a simple leaf-level module that registers its input.
54+
// This serves as a basic sequential element.
55+
module leaf4 (
56+
input clk,
57+
input in1,
58+
output out1
59+
);
60+
61+
DFF_X1 dff1 (.D(in1), .CK(clk), .Q(out1));
62+
63+
endmodule
64+
65+
// Defines a mid-level module that instantiates leaf1 and leaf2,
66+
// creating longer and more complex paths between them.
67+
module mid1 (
68+
input clk,
69+
input in1,
70+
input in2,
71+
output out1,
72+
output out2
73+
);
74+
75+
wire l1_out, l2_out1, l2_out2;
76+
77+
leaf1 u_leaf1 (
78+
.clk(clk),
79+
.in1(in1),
80+
.out1(l1_out)
81+
);
82+
83+
leaf2 u_leaf2 (
84+
.clk(clk),
85+
.in1(in2),
86+
.out1(l2_out1),
87+
.out2(l2_out2)
88+
);
89+
90+
DFF_X1 dff_out1 (.D(l1_out), .CK(clk), .Q(out1));
91+
DFF_X1 dff_out2 (.D(l2_out1), .CK(clk), .Q(out2));
92+
DFF_X1 dff_load1 (.D(l2_out1), .CK(clk), .Q());
93+
DFF_X1 dff_load2 (.D(l2_out1), .CK(clk), .Q());
94+
DFF_X1 dff_load3 (.D(l2_out1), .CK(clk), .Q());
95+
DFF_X1 dff_load4 (.D(l2_out1), .CK(clk), .Q());
96+
DFF_X1 dff_load5 (.D(l2_out1), .CK(clk), .Q());
97+
DFF_X1 dff_load6 (.D(l2_out1), .CK(clk), .Q());
98+
DFF_X1 dff_load7 (.D(l2_out1), .CK(clk), .Q());
99+
DFF_X1 dff_load8 (.D(l2_out1), .CK(clk), .Q());
100+
DFF_X1 dff_load9 (.D(l2_out1), .CK(clk), .Q());
101+
DFF_X1 dff_load10 (.D(l2_out1), .CK(clk), .Q());
102+
103+
endmodule
104+
105+
// Defines another mid-level module that instantiates leaf3 and leaf4,
106+
// combining their paths.
107+
module mid2 (
108+
input clk,
109+
input in1,
110+
input in2,
111+
output out1
112+
);
113+
114+
wire l3_out, l4_out;
115+
116+
leaf3 u_leaf3 (
117+
.clk(clk),
118+
.in1(in1),
119+
.out1(l3_out)
120+
);
121+
122+
leaf4 u_leaf4 (
123+
.clk(clk),
124+
.in1(in2),
125+
.out1(l4_out)
126+
);
127+
128+
wire n1;
129+
BUF_X1 buf1 (.A(l3_out), .Z(n1));
130+
DFF_X1 dff_out1 (.D(n1), .CK(clk), .Q(out1));
131+
132+
endmodule
133+
134+
// Defines the top-level module that instantiates the mid-level modules,
135+
// creating the final hierarchical structure with various timing paths.
136+
module top (
137+
input clk,
138+
input in1,
139+
input in2,
140+
input in3,
141+
input in4,
142+
output out1,
143+
output out2
144+
);
145+
146+
wire m1_out1, m1_out2, m2_out1;
147+
148+
mid1 u_mid1 (
149+
.clk(clk),
150+
.in1(in1),
151+
.in2(in2),
152+
.out1(m1_out1),
153+
.out2(m1_out2)
154+
);
155+
156+
mid2 u_mid2 (
157+
.clk(clk),
158+
.in1(in3),
159+
.in2(in4),
160+
.out1(m2_out1)
161+
);
162+
163+
wire n1, n2;
164+
BUF_X1 buf1 (.A(m1_out1), .Z(n1));
165+
BUF_X1 buf2 (.A(m2_out1), .Z(n2));
166+
167+
DFF_X1 dff_out1 (.D(n1), .CK(clk), .Q(out1));
168+
DFF_X1 dff_out2 (.D(n2), .CK(clk), .Q(out2));
169+
170+
endmodule

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