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eder-matheuseder-matheus
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rsz: update unit tests
Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
1 parent 0f63bad commit 6766db1

9 files changed

Lines changed: 75 additions & 57 deletions

‎src/rsz/test/buffer_ports10.defok‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -81,29 +81,29 @@ TRACKS Y 3340 DO 62 STEP 3200 LAYER metal9 ;
8181
TRACKS X 3390 DO 62 STEP 3200 LAYER metal10 ;
8282
TRACKS Y 3340 DO 62 STEP 3200 LAYER metal10 ;
8383
COMPONENTS 5 ;
84-
- input1 BUF_X1 + SOURCE TIMING + PLACED ( 20140 22400 ) N ;
85-
- input2 BUF_X1 + SOURCE TIMING + PLACED ( 20140 171500 ) N ;
86-
- output3 BUF_X1 + SOURCE TIMING + PLACED ( 178600 176400 ) N ;
87-
- output4 BUF_X1 + SOURCE TIMING + PLACED ( 178600 28140 ) N ;
88-
- r1 DFF_X1 + PLACED ( 23963 98140 ) N ;
84+
- input1 BUF_X1 + SOURCE TIMING + PLACED ( 101270 176400 ) N ;
85+
- input2 BUF_X1 + SOURCE TIMING + PLACED ( 99750 176400 ) N ;
86+
- output3 BUF_X1 + SOURCE TIMING + PLACED ( 100510 176400 ) N ;
87+
- output4 BUF_X1 + SOURCE TIMING + PLACED ( 98990 176400 ) N ;
88+
- r1 DFF_X1 + PLACED ( 96726 170871 ) N ;
8989
END COMPONENTS
9090
PINS 4 ;
9191
- clk1 + NET clk1 + DIRECTION INPUT + USE SIGNAL
9292
+ PORT
9393
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
94-
+ PLACED ( 2470 70 ) N ;
94+
+ PLACED ( 101270 199930 ) N ;
9595
- in1 + NET in1 + DIRECTION INPUT + USE SIGNAL
9696
+ PORT
97-
+ LAYER metal3 ( -70 -70 ) ( 70 70 )
98-
+ PLACED ( 70 171500 ) N ;
97+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
98+
+ PLACED ( 99750 199930 ) N ;
9999
- out1 + NET out1 + DIRECTION OUTPUT + USE SIGNAL
100100
+ PORT
101101
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
102-
+ PLACED ( 197030 199930 ) N ;
102+
+ PLACED ( 100510 199930 ) N ;
103103
- out2 + NET net3 + DIRECTION OUTPUT + USE SIGNAL
104104
+ PORT
105-
+ LAYER metal3 ( -70 -70 ) ( 70 70 )
106-
+ PLACED ( 199930 28140 ) N ;
105+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
106+
+ PLACED ( 98990 199930 ) N ;
107107
END PINS
108108
NETS 7 ;
109109
- clk1 ( PIN clk1 ) ( input1 A ) + USE SIGNAL ;

‎src/rsz/test/buffer_ports10.ok‎

Lines changed: 13 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,13 @@
33
[INFO IFP-0001] Added 56 rows of 420 site FreePDK45_38x28_10R_NP_162NW_34O.
44
Found 0 macro blocks.
55
Using 2 tracks default min distance between IO pins.
6-
[INFO PPL-0007] Random pin placement.
6+
[INFO PPL-0001] Number of available slots 1212
7+
[INFO PPL-0002] Number of I/O 4
8+
[INFO PPL-0003] Number of I/O w/sink 4
9+
[INFO PPL-0004] Number of I/O w/o sink 0
10+
[INFO PPL-0005] Slots per section 200
11+
[INFO PPL-0008] Successfully assigned pins to sections.
12+
[INFO PPL-0012] I/O nets HPWL: 201.52 um.
713
[INFO GPL-0002] DBU: 2000
814
[INFO GPL-0003] SiteSize: ( 0.190 1.400 ) um
915
[INFO GPL-0004] CoreBBox: ( 10.070 11.200 ) ( 89.870 89.600 ) um
@@ -21,11 +27,11 @@ Using 2 tracks default min distance between IO pins.
2127
[INFO GPL-0019] Utilization: 0.072 %
2228
[INFO GPL-0020] Standard cells area: 4.522 um^2
2329
[INFO GPL-0021] Large instances area: 0.000 um^2
24-
[InitialPlace] Iter: 1 conjugate gradient residual: 0.00000008 HPWL: 587290
25-
[InitialPlace] Iter: 2 conjugate gradient residual: 0.00000008 HPWL: 621160
26-
[InitialPlace] Iter: 3 conjugate gradient residual: 0.00000008 HPWL: 595065
27-
[InitialPlace] Iter: 4 conjugate gradient residual: 0.00000008 HPWL: 577570
28-
[InitialPlace] Iter: 5 conjugate gradient residual: 0.00000008 HPWL: 567244
30+
[InitialPlace] Iter: 1 conjugate gradient residual: 0.00000000 HPWL: 901740
31+
[InitialPlace] Iter: 2 conjugate gradient residual: 0.00000000 HPWL: 27780
32+
[InitialPlace] Iter: 3 conjugate gradient residual: 0.00000000 HPWL: 27780
33+
[InitialPlace] Iter: 4 conjugate gradient residual: 0.00000000 HPWL: 27780
34+
[InitialPlace] Iter: 5 conjugate gradient residual: 0.00000000 HPWL: 27780
2935
[INFO GPL-0023] Placement target density: 0.7000
3036
[INFO GPL-0024] Movable insts average area: 4.522 um^2
3137
[INFO GPL-0025] Ideal bin area: 6.460 um^2
@@ -37,7 +43,7 @@ Using 2 tracks default min distance between IO pins.
3743
[INFO GPL-0031] HPWL: Half-Perimeter Wirelength
3844
Iteration | Overflow | HPWL (um) | HPWL(%) | Penalty | Group
3945
---------------------------------------------------------------
40-
1 | 0.0000 | 5.633130e+05 | +0.00% | 9.92e-15 |
46+
1 | 0.0000 | 8.989100e+04 | +0.00% | 3.71e-14 |
4147
[INFO GPL-1001] Finished with Overflow: 0.000000
4248
[INFO GPL-1002] Placed Cell Area 4.5220
4349
[INFO GPL-1003] Available Free Area 6256.3200

‎src/rsz/test/buffer_ports10.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ initialize_floorplan -site $site \
1212

1313
source $tracks_file
1414

15-
place_pins -random -hor_layers $io_placer_hor_layer \
15+
place_pins -hor_layers $io_placer_hor_layer \
1616
-ver_layers $io_placer_ver_layer
1717

1818
global_placement

‎src/rsz/test/buffer_ports8.defok‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -81,29 +81,29 @@ TRACKS Y 3340 DO 62 STEP 3200 LAYER metal9 ;
8181
TRACKS X 3390 DO 62 STEP 3200 LAYER metal10 ;
8282
TRACKS Y 3340 DO 62 STEP 3200 LAYER metal10 ;
8383
COMPONENTS 5 ;
84-
- input1 BUF_X1 + SOURCE TIMING + PLACED ( 20140 22400 ) N ;
85-
- input2 BUF_X1 + SOURCE TIMING + PLACED ( 20140 171500 ) N ;
86-
- output3 BUF_X1 + SOURCE TIMING + PLACED ( 178600 176400 ) N ;
87-
- output4 BUF_X1 + SOURCE TIMING + PLACED ( 178600 28140 ) N ;
88-
- r1 DFF_X1 + PLACED ( 23963 98140 ) N ;
84+
- input1 BUF_X1 + SOURCE TIMING + PLACED ( 101270 176400 ) N ;
85+
- input2 BUF_X1 + SOURCE TIMING + PLACED ( 99750 176400 ) N ;
86+
- output3 BUF_X1 + SOURCE TIMING + PLACED ( 100510 176400 ) N ;
87+
- output4 BUF_X1 + SOURCE TIMING + PLACED ( 98990 176400 ) N ;
88+
- r1 DFF_X1 + PLACED ( 96726 170871 ) N ;
8989
END COMPONENTS
9090
PINS 4 ;
9191
- clk1 + NET clk1 + DIRECTION INPUT + USE SIGNAL
9292
+ PORT
9393
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
94-
+ PLACED ( 2470 70 ) N ;
94+
+ PLACED ( 101270 199930 ) N ;
9595
- in1 + NET in1 + DIRECTION INPUT + USE SIGNAL
9696
+ PORT
97-
+ LAYER metal3 ( -70 -70 ) ( 70 70 )
98-
+ PLACED ( 70 171500 ) N ;
97+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
98+
+ PLACED ( 99750 199930 ) N ;
9999
- out1 + NET out1 + DIRECTION OUTPUT + USE SIGNAL
100100
+ PORT
101101
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
102-
+ PLACED ( 197030 199930 ) N ;
102+
+ PLACED ( 100510 199930 ) N ;
103103
- out2 + NET net3 + DIRECTION OUTPUT + USE SIGNAL
104104
+ PORT
105-
+ LAYER metal3 ( -70 -70 ) ( 70 70 )
106-
+ PLACED ( 199930 28140 ) N ;
105+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
106+
+ PLACED ( 98990 199930 ) N ;
107107
END PINS
108108
NETS 7 ;
109109
- clk1 ( PIN clk1 ) ( input1 A ) + USE SIGNAL ;

‎src/rsz/test/buffer_ports8.ok‎

Lines changed: 13 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,13 @@
33
[INFO IFP-0001] Added 56 rows of 420 site FreePDK45_38x28_10R_NP_162NW_34O.
44
Found 0 macro blocks.
55
Using 2 tracks default min distance between IO pins.
6-
[INFO PPL-0007] Random pin placement.
6+
[INFO PPL-0001] Number of available slots 1212
7+
[INFO PPL-0002] Number of I/O 4
8+
[INFO PPL-0003] Number of I/O w/sink 4
9+
[INFO PPL-0004] Number of I/O w/o sink 0
10+
[INFO PPL-0005] Slots per section 200
11+
[INFO PPL-0008] Successfully assigned pins to sections.
12+
[INFO PPL-0012] I/O nets HPWL: 201.52 um.
713
[INFO GPL-0002] DBU: 2000
814
[INFO GPL-0003] SiteSize: ( 0.190 1.400 ) um
915
[INFO GPL-0004] CoreBBox: ( 10.070 11.200 ) ( 89.870 89.600 ) um
@@ -21,11 +27,11 @@ Using 2 tracks default min distance between IO pins.
2127
[INFO GPL-0019] Utilization: 0.072 %
2228
[INFO GPL-0020] Standard cells area: 4.522 um^2
2329
[INFO GPL-0021] Large instances area: 0.000 um^2
24-
[InitialPlace] Iter: 1 conjugate gradient residual: 0.00000008 HPWL: 587290
25-
[InitialPlace] Iter: 2 conjugate gradient residual: 0.00000008 HPWL: 621160
26-
[InitialPlace] Iter: 3 conjugate gradient residual: 0.00000008 HPWL: 595065
27-
[InitialPlace] Iter: 4 conjugate gradient residual: 0.00000008 HPWL: 577570
28-
[InitialPlace] Iter: 5 conjugate gradient residual: 0.00000008 HPWL: 567244
30+
[InitialPlace] Iter: 1 conjugate gradient residual: 0.00000000 HPWL: 901740
31+
[InitialPlace] Iter: 2 conjugate gradient residual: 0.00000000 HPWL: 27780
32+
[InitialPlace] Iter: 3 conjugate gradient residual: 0.00000000 HPWL: 27780
33+
[InitialPlace] Iter: 4 conjugate gradient residual: 0.00000000 HPWL: 27780
34+
[InitialPlace] Iter: 5 conjugate gradient residual: 0.00000000 HPWL: 27780
2935
[INFO GPL-0023] Placement target density: 0.7000
3036
[INFO GPL-0024] Movable insts average area: 4.522 um^2
3137
[INFO GPL-0025] Ideal bin area: 6.460 um^2
@@ -37,7 +43,7 @@ Using 2 tracks default min distance between IO pins.
3743
[INFO GPL-0031] HPWL: Half-Perimeter Wirelength
3844
Iteration | Overflow | HPWL (um) | HPWL(%) | Penalty | Group
3945
---------------------------------------------------------------
40-
1 | 0.0000 | 5.633130e+05 | +0.00% | 9.92e-15 |
46+
1 | 0.0000 | 8.989100e+04 | +0.00% | 3.71e-14 |
4147
[INFO GPL-1001] Finished with Overflow: 0.000000
4248
[INFO GPL-1002] Placed Cell Area 4.5220
4349
[INFO GPL-1003] Available Free Area 6256.3200

‎src/rsz/test/buffer_ports8.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ initialize_floorplan -site $site \
1212

1313
source $tracks_file
1414

15-
place_pins -random -hor_layers $io_placer_hor_layer \
15+
place_pins -hor_layers $io_placer_hor_layer \
1616
-ver_layers $io_placer_ver_layer
1717

1818
global_placement

‎src/rsz/test/buffer_ports9.defok‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -81,29 +81,29 @@ TRACKS Y 3340 DO 62 STEP 3200 LAYER metal9 ;
8181
TRACKS X 3390 DO 62 STEP 3200 LAYER metal10 ;
8282
TRACKS Y 3340 DO 62 STEP 3200 LAYER metal10 ;
8383
COMPONENTS 5 ;
84-
- input1 BUF_X16 + SOURCE TIMING + PLACED ( 20140 22400 ) N ;
85-
- input2 BUF_X16 + SOURCE TIMING + PLACED ( 20140 171500 ) N ;
86-
- output3 BUF_X16 + SOURCE TIMING + PLACED ( 170240 176400 ) N ;
87-
- output4 BUF_X16 + SOURCE TIMING + PLACED ( 170240 28140 ) N ;
88-
- r1 DFF_X1 + PLACED ( 23963 98140 ) N ;
84+
- input1 BUF_X16 + SOURCE TIMING + PLACED ( 101270 176400 ) N ;
85+
- input2 BUF_X16 + SOURCE TIMING + PLACED ( 99750 176400 ) N ;
86+
- output3 BUF_X16 + SOURCE TIMING + PLACED ( 100510 176400 ) N ;
87+
- output4 BUF_X16 + SOURCE TIMING + PLACED ( 98990 176400 ) N ;
88+
- r1 DFF_X1 + PLACED ( 96726 170871 ) N ;
8989
END COMPONENTS
9090
PINS 4 ;
9191
- clk1 + NET clk1 + DIRECTION INPUT + USE SIGNAL
9292
+ PORT
9393
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
94-
+ PLACED ( 2470 70 ) N ;
94+
+ PLACED ( 101270 199930 ) N ;
9595
- in1 + NET in1 + DIRECTION INPUT + USE SIGNAL
9696
+ PORT
97-
+ LAYER metal3 ( -70 -70 ) ( 70 70 )
98-
+ PLACED ( 70 171500 ) N ;
97+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
98+
+ PLACED ( 99750 199930 ) N ;
9999
- out1 + NET out1 + DIRECTION OUTPUT + USE SIGNAL
100100
+ PORT
101101
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
102-
+ PLACED ( 197030 199930 ) N ;
102+
+ PLACED ( 100510 199930 ) N ;
103103
- out2 + NET net3 + DIRECTION OUTPUT + USE SIGNAL
104104
+ PORT
105-
+ LAYER metal3 ( -70 -70 ) ( 70 70 )
106-
+ PLACED ( 199930 28140 ) N ;
105+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
106+
+ PLACED ( 98990 199930 ) N ;
107107
END PINS
108108
NETS 7 ;
109109
- clk1 ( PIN clk1 ) ( input1 A ) + USE SIGNAL ;

‎src/rsz/test/buffer_ports9.ok‎

Lines changed: 13 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,13 @@
33
[INFO IFP-0001] Added 56 rows of 420 site FreePDK45_38x28_10R_NP_162NW_34O.
44
Found 0 macro blocks.
55
Using 2 tracks default min distance between IO pins.
6-
[INFO PPL-0007] Random pin placement.
6+
[INFO PPL-0001] Number of available slots 1212
7+
[INFO PPL-0002] Number of I/O 4
8+
[INFO PPL-0003] Number of I/O w/sink 4
9+
[INFO PPL-0004] Number of I/O w/o sink 0
10+
[INFO PPL-0005] Slots per section 200
11+
[INFO PPL-0008] Successfully assigned pins to sections.
12+
[INFO PPL-0012] I/O nets HPWL: 201.52 um.
713
[INFO GPL-0002] DBU: 2000
814
[INFO GPL-0003] SiteSize: ( 0.190 1.400 ) um
915
[INFO GPL-0004] CoreBBox: ( 10.070 11.200 ) ( 89.870 89.600 ) um
@@ -21,11 +27,11 @@ Using 2 tracks default min distance between IO pins.
2127
[INFO GPL-0019] Utilization: 0.072 %
2228
[INFO GPL-0020] Standard cells area: 4.522 um^2
2329
[INFO GPL-0021] Large instances area: 0.000 um^2
24-
[InitialPlace] Iter: 1 conjugate gradient residual: 0.00000008 HPWL: 587290
25-
[InitialPlace] Iter: 2 conjugate gradient residual: 0.00000008 HPWL: 621160
26-
[InitialPlace] Iter: 3 conjugate gradient residual: 0.00000008 HPWL: 595065
27-
[InitialPlace] Iter: 4 conjugate gradient residual: 0.00000008 HPWL: 577570
28-
[InitialPlace] Iter: 5 conjugate gradient residual: 0.00000008 HPWL: 567244
30+
[InitialPlace] Iter: 1 conjugate gradient residual: 0.00000000 HPWL: 901740
31+
[InitialPlace] Iter: 2 conjugate gradient residual: 0.00000000 HPWL: 27780
32+
[InitialPlace] Iter: 3 conjugate gradient residual: 0.00000000 HPWL: 27780
33+
[InitialPlace] Iter: 4 conjugate gradient residual: 0.00000000 HPWL: 27780
34+
[InitialPlace] Iter: 5 conjugate gradient residual: 0.00000000 HPWL: 27780
2935
[INFO GPL-0023] Placement target density: 0.7000
3036
[INFO GPL-0024] Movable insts average area: 4.522 um^2
3137
[INFO GPL-0025] Ideal bin area: 6.460 um^2
@@ -37,7 +43,7 @@ Using 2 tracks default min distance between IO pins.
3743
[INFO GPL-0031] HPWL: Half-Perimeter Wirelength
3844
Iteration | Overflow | HPWL (um) | HPWL(%) | Penalty | Group
3945
---------------------------------------------------------------
40-
1 | 0.0000 | 5.633130e+05 | +0.00% | 9.92e-15 |
46+
1 | 0.0000 | 8.989100e+04 | +0.00% | 3.71e-14 |
4147
[INFO GPL-1001] Finished with Overflow: 0.000000
4248
[INFO GPL-1002] Placed Cell Area 4.5220
4349
[INFO GPL-1003] Available Free Area 6256.3200

‎src/rsz/test/buffer_ports9.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ initialize_floorplan -site $site \
1212

1313
source $tracks_file
1414

15-
place_pins -random -hor_layers $io_placer_hor_layer \
15+
place_pins -hor_layers $io_placer_hor_layer \
1616
-ver_layers $io_placer_ver_layer
1717

1818
global_placement

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