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Expand file tree Collapse file tree Original file line number Diff line number Diff line change @@ -74,6 +74,21 @@ proc run_equivalence_test { test lib remove_cells } {
7474 # tclint-disable-next-line line-length
7575 puts $outfile " \[ gate]\n read_verilog -sv $after_netlist $lib_files \n prep -top $top_cell -flatten\n memory_map\n\n "
7676
77+ # Recommendation from eqy team on how to speed up a design
78+ puts $outfile " \[ match *]\n gate-nomatch _*_.*"
79+
80+ # See issue OpenROAD#6545 "Equivalence check failure due to non-unique resizer nets"
81+ puts $outfile " gate-nomatch net*"
82+
83+ # Forbid matching on buffer instances or cloned instances to make it less
84+ # likely EQY will fail to prove equivalence because of its assuming structural
85+ # similarity between gold and gate netlists. This doesn't remove coverage.
86+ puts $outfile " gate-nomatch clone*"
87+ puts $outfile " gate-nomatch place*"
88+ puts $outfile " gate-nomatch rebuffer*"
89+ puts $outfile " gate-nomatch wire*"
90+ puts $outfile " gate-nomatch place*\n\n "
91+
7792 # Equivalence check recipe
7893 puts $outfile " \[ strategy basic]\n use sat\n depth 10\n\n "
7994 close $outfile
@@ -83,9 +98,9 @@ proc run_equivalence_test { test lib remove_cells } {
8398 catch { exec eqy -d $run_dir $test_script > /dev/null }
8499 set count 0
85100 catch {
86- set count [
87- exec grep -c " Successfully proved designs equivalent"
88- $run_dir /logfile.txt
101+ set count [ \
102+ exec grep -c " Successfully proved designs equivalent" \
103+ $run_dir /logfile.txt \
89104 ]
90105 }
91106 if { $count == 0 } {
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