|
| 1 | +from openroad import Tech, Design |
| 2 | +import odb |
| 3 | +import helpers |
| 4 | +import ifp_helpers as ifph |
| 5 | + |
| 6 | +tech = Tech() |
| 7 | +tech.readLef("Nangate45/Nangate45.lef") |
| 8 | +tech.readLef("init_floorplan_gap.lef") |
| 9 | +tech.readLiberty("Nangate45/Nangate45_typ.lib") |
| 10 | + |
| 11 | +design = Design(tech) |
| 12 | +design.readVerilog("reg1.v") |
| 13 | +design.link("top") |
| 14 | + |
| 15 | +die = helpers.make_rect(design, 0, 0, 100, 100) |
| 16 | +core = helpers.make_rect(design, 0, 0, 100, 100) |
| 17 | + |
| 18 | +l = design.micronToDBU(34) |
| 19 | +u = design.micronToDBU(66) |
| 20 | + |
| 21 | +ifph.create_voltage_domain(design, "TEMP_ANALOG", (l, l, u, u)) |
| 22 | + |
| 23 | +floorplan = design.getFloorplan() |
| 24 | +site = floorplan.findSite("FreePDK45_38x28_10R_NP_162NW_34O") |
| 25 | +additional_site = floorplan.findSite("FreePDK45_38x28_10R_NP_162NW_34O_DoubleHeight") |
| 26 | +floorplan.initFloorplan( |
| 27 | + die, core, site, [additional_site], "NONE", [], design.micronToDBU(2) |
| 28 | +) |
| 29 | +def_file = helpers.make_result_file("init_floorplan_gap.def") |
| 30 | +design.writeDef(def_file) |
| 31 | +helpers.diff_files("init_floorplan_gap.defok", def_file) |
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