Skip to content

Commit 930ee1c

Browse files
jhkim-piijhkim-pii
committed
rsz: Added a new "-verbose" argument for "buffer_ports" command.
1 parent 563b0b9 commit 930ee1c

10 files changed

Lines changed: 273 additions & 18 deletions

File tree

‎src/rsz/README.md‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -224,6 +224,8 @@ buffer_ports
224224
| ----- | ----- |
225225
| `-inputs`, `-outputs` | Insert a buffer between the input and load, output and load respectively. The default behavior is `-inputs` and `-outputs` set if neither is specified. |
226226
| `-max_utilization` | Defines the percentage of core area used. |
227+
| `-buffer_cell` | Specifies the buffer cell type to be used. |
228+
| `-verbose` | Enable verbose logging. |
227229

228230
#### Instance Name Prefixes
229231

‎src/rsz/include/rsz/Resizer.hh‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -259,8 +259,8 @@ class Resizer : public dbStaState, public dbNetworkObserver
259259
// Remove all or selected buffers from the netlist.
260260
void removeBuffers(InstanceSeq insts);
261261
void unbufferNet(Net* net);
262-
void bufferInputs(LibertyCell* buffer_cell = nullptr);
263-
void bufferOutputs(LibertyCell* buffer_cell = nullptr);
262+
void bufferInputs(LibertyCell* buffer_cell = nullptr, bool verbose = false);
263+
void bufferOutputs(LibertyCell* buffer_cell = nullptr, bool verbose = false);
264264

265265
// from sta::dbNetworkObserver callbacks
266266
void postReadLiberty() override;
@@ -446,8 +446,10 @@ class Resizer : public dbStaState, public dbNetworkObserver
446446
double computeDesignArea();
447447
void initDesignArea();
448448
void ensureLevelDrvrVertices();
449-
Instance* bufferInput(const Pin* top_pin, LibertyCell* buffer_cell);
450-
void bufferOutput(const Pin* top_pin, LibertyCell* buffer_cell);
449+
Instance* bufferInput(const Pin* top_pin,
450+
LibertyCell* buffer_cell,
451+
bool verbose);
452+
void bufferOutput(const Pin* top_pin, LibertyCell* buffer_cell, bool verbose);
451453
bool hasTristateOrDontTouchDriver(const Net* net);
452454
bool isTristateDriver(const Pin* pin);
453455
void checkLibertyForAllCorners();

‎src/rsz/src/Resizer.cc‎

Lines changed: 40 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -771,7 +771,7 @@ bool Resizer::isLinkCell(LibertyCell* cell) const
771771

772772
////////////////////////////////////////////////////////////////
773773

774-
void Resizer::bufferInputs(LibertyCell* buffer_cell)
774+
void Resizer::bufferInputs(LibertyCell* buffer_cell, bool verbose)
775775
{
776776
init();
777777

@@ -781,6 +781,13 @@ void Resizer::bufferInputs(LibertyCell* buffer_cell)
781781
return;
782782
}
783783

784+
if (verbose) {
785+
logger_->info(RSZ,
786+
29,
787+
"Start input port buffering with {}.",
788+
selected_buffer_cell->name());
789+
}
790+
784791
sta_->ensureClkNetwork();
785792
inserted_buffer_count_ = 0;
786793
buffer_moved_into_core_ = false;
@@ -800,7 +807,7 @@ void Resizer::bufferInputs(LibertyCell* buffer_cell)
800807
// Hands off special nets.
801808
&& !db_network_->isSpecial(net) && hasPins(net)) {
802809
// repair_design will resize to target slew.
803-
bufferInput(pin, selected_buffer_cell);
810+
bufferInput(pin, selected_buffer_cell, verbose);
804811
}
805812
}
806813
}
@@ -880,7 +887,9 @@ void Resizer::SwapNetNames(odb::dbITerm* iterm_to, odb::dbITerm* iterm_from)
880887
Make sure all the top pins are buffered
881888
*/
882889

883-
Instance* Resizer::bufferInput(const Pin* top_pin, LibertyCell* buffer_cell)
890+
Instance* Resizer::bufferInput(const Pin* top_pin,
891+
LibertyCell* buffer_cell,
892+
bool verbose)
884893
{
885894
dbNet* top_pin_flat_net = db_network_->flatNet(top_pin);
886895
odb::dbModNet* top_pin_hier_net = db_network_->hierNet(top_pin);
@@ -925,9 +934,20 @@ Instance* Resizer::bufferInput(const Pin* top_pin, LibertyCell* buffer_cell)
925934
delete pin_iter;
926935
// dont buffer, buffers
927936
if (has_dont_touch || !has_non_buffer) {
937+
if (verbose) {
938+
logger_->info(RSZ,
939+
213,
940+
"Skipping input port {} buffering.",
941+
network_->name(top_pin));
942+
}
928943
return nullptr;
929944
}
930945

946+
if (verbose) {
947+
logger_->info(
948+
RSZ, 214, "Buffering input port {}.", network_->name(top_pin));
949+
}
950+
931951
// make the buffer and its output net.
932952
string buffer_name = makeUniqueInstName("input");
933953
Instance* parent = db_network_->topInstance();
@@ -1000,7 +1020,7 @@ Instance* Resizer::bufferInput(const Pin* top_pin, LibertyCell* buffer_cell)
10001020
return buffer;
10011021
}
10021022

1003-
void Resizer::bufferOutputs(LibertyCell* buffer_cell)
1023+
void Resizer::bufferOutputs(LibertyCell* buffer_cell, bool verbose)
10041024
{
10051025
init();
10061026

@@ -1010,6 +1030,13 @@ void Resizer::bufferOutputs(LibertyCell* buffer_cell)
10101030
return;
10111031
}
10121032

1033+
if (verbose) {
1034+
logger_->info(RSZ,
1035+
31,
1036+
"Start output port buffering with {}.",
1037+
selected_buffer_cell->name());
1038+
}
1039+
10131040
inserted_buffer_count_ = 0;
10141041
buffer_moved_into_core_ = false;
10151042

@@ -1029,7 +1056,7 @@ void Resizer::bufferOutputs(LibertyCell* buffer_cell)
10291056
// drivers.
10301057
&& !hasTristateOrDontTouchDriver(net) && !vertex->isConstant()
10311058
&& hasPins(net)) {
1032-
bufferOutput(pin, selected_buffer_cell);
1059+
bufferOutput(pin, selected_buffer_cell, verbose);
10331060
}
10341061
}
10351062
}
@@ -1077,8 +1104,15 @@ bool Resizer::isTristateDriver(const Pin* pin)
10771104
return port && port->direction()->isAnyTristate();
10781105
}
10791106

1080-
void Resizer::bufferOutput(const Pin* top_pin, LibertyCell* buffer_cell)
1107+
void Resizer::bufferOutput(const Pin* top_pin,
1108+
LibertyCell* buffer_cell,
1109+
bool verbose)
10811110
{
1111+
if (verbose) {
1112+
logger_->info(
1113+
RSZ, 215, "Buffering output port {}.", network_->name(top_pin));
1114+
}
1115+
10821116
NetworkEdit* network = networkEdit();
10831117

10841118
odb::dbITerm* top_pin_op_iterm;

‎src/rsz/src/Resizer.i‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
// SPDX-License-Identifier: BSD-3-Clause
22
// Copyright (c) 2019-2025, The OpenROAD Authors
33

4+
// clang-format off
5+
46
%{
57

68
#include <cstdint>
@@ -409,19 +411,19 @@ set_dont_touch_net(Net *net,
409411
}
410412

411413
void
412-
buffer_inputs(LibertyCell *buffer_cell)
414+
buffer_inputs(LibertyCell *buffer_cell, bool verbose)
413415
{
414416
ensureLinked();
415417
Resizer *resizer = getResizer();
416-
resizer->bufferInputs(buffer_cell);
418+
resizer->bufferInputs(buffer_cell, verbose);
417419
}
418420

419421
void
420-
buffer_outputs(LibertyCell *buffer_cell)
422+
buffer_outputs(LibertyCell *buffer_cell, bool verbose)
421423
{
422424
ensureLinked();
423425
Resizer *resizer = getResizer();
424-
resizer->bufferOutputs(buffer_cell);
426+
resizer->bufferOutputs(buffer_cell, verbose);
425427
}
426428

427429
void

‎src/rsz/src/Resizer.tcl‎

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -470,12 +470,13 @@ proc report_dont_touch { args } {
470470

471471
sta::define_cmd_args "buffer_ports" {[-inputs] [-outputs]\
472472
[-max_utilization util]\
473-
[-buffer_cell buf_cell]}
473+
[-buffer_cell buf_cell]\
474+
[-verbose]}
474475

475476
proc buffer_ports { args } {
476477
sta::parse_key_args "buffer_ports" args \
477478
keys {-buffer_cell -max_utilization} \
478-
flags {-inputs -outputs}
479+
flags {-inputs -outputs -verbose}
479480

480481
set buffer_inputs [info exists flags(-inputs)]
481482
set buffer_outputs [info exists flags(-outputs)]
@@ -484,16 +485,18 @@ proc buffer_ports { args } {
484485
set buffer_outputs 1
485486
}
486487

488+
set verbose [info exists flags(-verbose)]
489+
487490
sta::check_argc_eq0 "buffer_ports" $args
488491

489492
rsz::set_max_utilization [rsz::parse_max_util keys]
490493
set buffer_cell [rsz::parse_buffer_cell keys 0] ; # 0: optional argument
491494

492495
if { $buffer_inputs } {
493-
rsz::buffer_inputs $buffer_cell
496+
rsz::buffer_inputs $buffer_cell $verbose
494497
}
495498
if { $buffer_outputs } {
496-
rsz::buffer_outputs $buffer_cell
499+
rsz::buffer_outputs $buffer_cell $verbose
497500
}
498501
}
499502

‎src/rsz/test/CMakeLists.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@ or_integration_tests(
1313
buffer_ports7
1414
buffer_ports8
1515
buffer_ports9
16+
buffer_ports10
1617
buffer_varying_lengths
1718
clone_flat
1819
clone_hier

‎src/rsz/test/buffer_ports10.defok‎

Lines changed: 117 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,117 @@
1+
VERSION 5.8 ;
2+
DIVIDERCHAR "/" ;
3+
BUSBITCHARS "[]" ;
4+
DESIGN top ;
5+
UNITS DISTANCE MICRONS 2000 ;
6+
DIEAREA ( 0 0 ) ( 200000 200000 ) ;
7+
ROW ROW_0 FreePDK45_38x28_10R_NP_162NW_34O 20140 22400 N DO 420 BY 1 STEP 380 0 ;
8+
ROW ROW_1 FreePDK45_38x28_10R_NP_162NW_34O 20140 25200 FS DO 420 BY 1 STEP 380 0 ;
9+
ROW ROW_2 FreePDK45_38x28_10R_NP_162NW_34O 20140 28000 N DO 420 BY 1 STEP 380 0 ;
10+
ROW ROW_3 FreePDK45_38x28_10R_NP_162NW_34O 20140 30800 FS DO 420 BY 1 STEP 380 0 ;
11+
ROW ROW_4 FreePDK45_38x28_10R_NP_162NW_34O 20140 33600 N DO 420 BY 1 STEP 380 0 ;
12+
ROW ROW_5 FreePDK45_38x28_10R_NP_162NW_34O 20140 36400 FS DO 420 BY 1 STEP 380 0 ;
13+
ROW ROW_6 FreePDK45_38x28_10R_NP_162NW_34O 20140 39200 N DO 420 BY 1 STEP 380 0 ;
14+
ROW ROW_7 FreePDK45_38x28_10R_NP_162NW_34O 20140 42000 FS DO 420 BY 1 STEP 380 0 ;
15+
ROW ROW_8 FreePDK45_38x28_10R_NP_162NW_34O 20140 44800 N DO 420 BY 1 STEP 380 0 ;
16+
ROW ROW_9 FreePDK45_38x28_10R_NP_162NW_34O 20140 47600 FS DO 420 BY 1 STEP 380 0 ;
17+
ROW ROW_10 FreePDK45_38x28_10R_NP_162NW_34O 20140 50400 N DO 420 BY 1 STEP 380 0 ;
18+
ROW ROW_11 FreePDK45_38x28_10R_NP_162NW_34O 20140 53200 FS DO 420 BY 1 STEP 380 0 ;
19+
ROW ROW_12 FreePDK45_38x28_10R_NP_162NW_34O 20140 56000 N DO 420 BY 1 STEP 380 0 ;
20+
ROW ROW_13 FreePDK45_38x28_10R_NP_162NW_34O 20140 58800 FS DO 420 BY 1 STEP 380 0 ;
21+
ROW ROW_14 FreePDK45_38x28_10R_NP_162NW_34O 20140 61600 N DO 420 BY 1 STEP 380 0 ;
22+
ROW ROW_15 FreePDK45_38x28_10R_NP_162NW_34O 20140 64400 FS DO 420 BY 1 STEP 380 0 ;
23+
ROW ROW_16 FreePDK45_38x28_10R_NP_162NW_34O 20140 67200 N DO 420 BY 1 STEP 380 0 ;
24+
ROW ROW_17 FreePDK45_38x28_10R_NP_162NW_34O 20140 70000 FS DO 420 BY 1 STEP 380 0 ;
25+
ROW ROW_18 FreePDK45_38x28_10R_NP_162NW_34O 20140 72800 N DO 420 BY 1 STEP 380 0 ;
26+
ROW ROW_19 FreePDK45_38x28_10R_NP_162NW_34O 20140 75600 FS DO 420 BY 1 STEP 380 0 ;
27+
ROW ROW_20 FreePDK45_38x28_10R_NP_162NW_34O 20140 78400 N DO 420 BY 1 STEP 380 0 ;
28+
ROW ROW_21 FreePDK45_38x28_10R_NP_162NW_34O 20140 81200 FS DO 420 BY 1 STEP 380 0 ;
29+
ROW ROW_22 FreePDK45_38x28_10R_NP_162NW_34O 20140 84000 N DO 420 BY 1 STEP 380 0 ;
30+
ROW ROW_23 FreePDK45_38x28_10R_NP_162NW_34O 20140 86800 FS DO 420 BY 1 STEP 380 0 ;
31+
ROW ROW_24 FreePDK45_38x28_10R_NP_162NW_34O 20140 89600 N DO 420 BY 1 STEP 380 0 ;
32+
ROW ROW_25 FreePDK45_38x28_10R_NP_162NW_34O 20140 92400 FS DO 420 BY 1 STEP 380 0 ;
33+
ROW ROW_26 FreePDK45_38x28_10R_NP_162NW_34O 20140 95200 N DO 420 BY 1 STEP 380 0 ;
34+
ROW ROW_27 FreePDK45_38x28_10R_NP_162NW_34O 20140 98000 FS DO 420 BY 1 STEP 380 0 ;
35+
ROW ROW_28 FreePDK45_38x28_10R_NP_162NW_34O 20140 100800 N DO 420 BY 1 STEP 380 0 ;
36+
ROW ROW_29 FreePDK45_38x28_10R_NP_162NW_34O 20140 103600 FS DO 420 BY 1 STEP 380 0 ;
37+
ROW ROW_30 FreePDK45_38x28_10R_NP_162NW_34O 20140 106400 N DO 420 BY 1 STEP 380 0 ;
38+
ROW ROW_31 FreePDK45_38x28_10R_NP_162NW_34O 20140 109200 FS DO 420 BY 1 STEP 380 0 ;
39+
ROW ROW_32 FreePDK45_38x28_10R_NP_162NW_34O 20140 112000 N DO 420 BY 1 STEP 380 0 ;
40+
ROW ROW_33 FreePDK45_38x28_10R_NP_162NW_34O 20140 114800 FS DO 420 BY 1 STEP 380 0 ;
41+
ROW ROW_34 FreePDK45_38x28_10R_NP_162NW_34O 20140 117600 N DO 420 BY 1 STEP 380 0 ;
42+
ROW ROW_35 FreePDK45_38x28_10R_NP_162NW_34O 20140 120400 FS DO 420 BY 1 STEP 380 0 ;
43+
ROW ROW_36 FreePDK45_38x28_10R_NP_162NW_34O 20140 123200 N DO 420 BY 1 STEP 380 0 ;
44+
ROW ROW_37 FreePDK45_38x28_10R_NP_162NW_34O 20140 126000 FS DO 420 BY 1 STEP 380 0 ;
45+
ROW ROW_38 FreePDK45_38x28_10R_NP_162NW_34O 20140 128800 N DO 420 BY 1 STEP 380 0 ;
46+
ROW ROW_39 FreePDK45_38x28_10R_NP_162NW_34O 20140 131600 FS DO 420 BY 1 STEP 380 0 ;
47+
ROW ROW_40 FreePDK45_38x28_10R_NP_162NW_34O 20140 134400 N DO 420 BY 1 STEP 380 0 ;
48+
ROW ROW_41 FreePDK45_38x28_10R_NP_162NW_34O 20140 137200 FS DO 420 BY 1 STEP 380 0 ;
49+
ROW ROW_42 FreePDK45_38x28_10R_NP_162NW_34O 20140 140000 N DO 420 BY 1 STEP 380 0 ;
50+
ROW ROW_43 FreePDK45_38x28_10R_NP_162NW_34O 20140 142800 FS DO 420 BY 1 STEP 380 0 ;
51+
ROW ROW_44 FreePDK45_38x28_10R_NP_162NW_34O 20140 145600 N DO 420 BY 1 STEP 380 0 ;
52+
ROW ROW_45 FreePDK45_38x28_10R_NP_162NW_34O 20140 148400 FS DO 420 BY 1 STEP 380 0 ;
53+
ROW ROW_46 FreePDK45_38x28_10R_NP_162NW_34O 20140 151200 N DO 420 BY 1 STEP 380 0 ;
54+
ROW ROW_47 FreePDK45_38x28_10R_NP_162NW_34O 20140 154000 FS DO 420 BY 1 STEP 380 0 ;
55+
ROW ROW_48 FreePDK45_38x28_10R_NP_162NW_34O 20140 156800 N DO 420 BY 1 STEP 380 0 ;
56+
ROW ROW_49 FreePDK45_38x28_10R_NP_162NW_34O 20140 159600 FS DO 420 BY 1 STEP 380 0 ;
57+
ROW ROW_50 FreePDK45_38x28_10R_NP_162NW_34O 20140 162400 N DO 420 BY 1 STEP 380 0 ;
58+
ROW ROW_51 FreePDK45_38x28_10R_NP_162NW_34O 20140 165200 FS DO 420 BY 1 STEP 380 0 ;
59+
ROW ROW_52 FreePDK45_38x28_10R_NP_162NW_34O 20140 168000 N DO 420 BY 1 STEP 380 0 ;
60+
ROW ROW_53 FreePDK45_38x28_10R_NP_162NW_34O 20140 170800 FS DO 420 BY 1 STEP 380 0 ;
61+
ROW ROW_54 FreePDK45_38x28_10R_NP_162NW_34O 20140 173600 N DO 420 BY 1 STEP 380 0 ;
62+
ROW ROW_55 FreePDK45_38x28_10R_NP_162NW_34O 20140 176400 FS DO 420 BY 1 STEP 380 0 ;
63+
TRACKS X 190 DO 526 STEP 380 LAYER metal1 ;
64+
TRACKS Y 140 DO 714 STEP 280 LAYER metal1 ;
65+
TRACKS X 190 DO 526 STEP 380 LAYER metal2 ;
66+
TRACKS Y 140 DO 714 STEP 280 LAYER metal2 ;
67+
TRACKS X 190 DO 526 STEP 380 LAYER metal3 ;
68+
TRACKS Y 140 DO 714 STEP 280 LAYER metal3 ;
69+
TRACKS X 190 DO 357 STEP 560 LAYER metal4 ;
70+
TRACKS Y 140 DO 357 STEP 560 LAYER metal4 ;
71+
TRACKS X 190 DO 357 STEP 560 LAYER metal5 ;
72+
TRACKS Y 140 DO 357 STEP 560 LAYER metal5 ;
73+
TRACKS X 190 DO 357 STEP 560 LAYER metal6 ;
74+
TRACKS Y 140 DO 357 STEP 560 LAYER metal6 ;
75+
TRACKS X 1790 DO 124 STEP 1600 LAYER metal7 ;
76+
TRACKS Y 1740 DO 124 STEP 1600 LAYER metal7 ;
77+
TRACKS X 1790 DO 124 STEP 1600 LAYER metal8 ;
78+
TRACKS Y 1740 DO 124 STEP 1600 LAYER metal8 ;
79+
TRACKS X 3390 DO 62 STEP 3200 LAYER metal9 ;
80+
TRACKS Y 3340 DO 62 STEP 3200 LAYER metal9 ;
81+
TRACKS X 3390 DO 62 STEP 3200 LAYER metal10 ;
82+
TRACKS Y 3340 DO 62 STEP 3200 LAYER metal10 ;
83+
COMPONENTS 5 ;
84+
- input1 BUF_X16 + SOURCE TIMING + PLACED ( 20140 22400 ) N ;
85+
- input2 BUF_X16 + SOURCE TIMING + PLACED ( 20140 171500 ) N ;
86+
- output3 BUF_X16 + SOURCE TIMING + PLACED ( 170240 176400 ) N ;
87+
- output4 BUF_X16 + SOURCE TIMING + PLACED ( 170240 28140 ) N ;
88+
- r1 DFF_X1 + PLACED ( 23963 98140 ) N ;
89+
END COMPONENTS
90+
PINS 4 ;
91+
- clk1 + NET clk1 + DIRECTION INPUT + USE SIGNAL
92+
+ PORT
93+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
94+
+ PLACED ( 2470 70 ) N ;
95+
- in1 + NET in1 + DIRECTION INPUT + USE SIGNAL
96+
+ PORT
97+
+ LAYER metal3 ( -70 -70 ) ( 70 70 )
98+
+ PLACED ( 70 171500 ) N ;
99+
- out1 + NET out1 + DIRECTION OUTPUT + USE SIGNAL
100+
+ PORT
101+
+ LAYER metal2 ( -70 -70 ) ( 70 70 )
102+
+ PLACED ( 197030 199930 ) N ;
103+
- out2 + NET net3 + DIRECTION OUTPUT + USE SIGNAL
104+
+ PORT
105+
+ LAYER metal3 ( -70 -70 ) ( 70 70 )
106+
+ PLACED ( 199930 28140 ) N ;
107+
END PINS
108+
NETS 7 ;
109+
- clk1 ( PIN clk1 ) ( input1 A ) + USE SIGNAL ;
110+
- in1 ( PIN in1 ) ( input2 A ) + USE SIGNAL ;
111+
- net1 ( input1 Z ) ( r1 CK ) + USE SIGNAL ;
112+
- net2 ( input2 Z ) ( r1 D ) + USE SIGNAL ;
113+
- net3 ( PIN out2 ) ( output4 Z ) + USE SIGNAL ;
114+
- net4 ( output4 A ) ( output3 A ) ( r1 Q ) + USE SIGNAL ;
115+
- out1 ( PIN out1 ) ( output3 Z ) + USE SIGNAL ;
116+
END NETS
117+
END DESIGN

0 commit comments

Comments
 (0)