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jhkim-piijhkim-pii
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Added new regressions
Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
1 parent 6d7b7ad commit 9d06a6b

11 files changed

Lines changed: 8602 additions & 0 deletions

‎src/cts/test/CMakeLists.txt‎

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@@ -20,6 +20,8 @@ or_integration_tests(
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check_max_fanout3
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check_wire_rc_cts
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dummy_load
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escape_slash
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escape_slash_hier
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find_clock
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find_clock_pad
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gated_clock1

‎src/cts/test/escape_slash.ok‎

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[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
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[INFO IFP-0001] Added 714 rows of 5263 site FreePDK45_38x28_10R_NP_162NW_34O.
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Found 0 macro blocks.
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Using 2 tracks default min distance between IO pins.
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[INFO PPL-0001] Number of available slots 12380
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[INFO PPL-0002] Number of I/O 1
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[INFO PPL-0003] Number of I/O w/sink 1
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[INFO PPL-0004] Number of I/O w/o sink 0
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[INFO PPL-0005] Slots per section 200
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[INFO PPL-0008] Successfully assigned pins to sections.
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[INFO PPL-0012] I/O nets HPWL: 500.17 um.
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[INFO GPL-0005] Execute conjugate gradient initial placement.
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[INFO GPL-0002] DBU: 2000
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[INFO GPL-0003] SiteSize: ( 0.190 1.400 ) um
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[INFO GPL-0004] CoreBBox: ( 0.000 0.000 ) ( 999.970 999.600 ) um
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[INFO GPL-0006] Number of instances: 283
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[INFO GPL-0007] Movable instances: 283
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[INFO GPL-0008] Fixed instances: 0
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[INFO GPL-0009] Dummy instances: 0
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[INFO GPL-0010] Number of nets: 6
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[INFO GPL-0011] Number of pins: 289
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[INFO GPL-0012] Die BBox: ( 0.000 0.000 ) ( 1000.000 1000.000 ) um
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[INFO GPL-0013] Core BBox: ( 0.000 0.000 ) ( 999.970 999.600 ) um
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[INFO GPL-0016] Core area: 999570.012 um^2
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[INFO GPL-0017] Fixed instances area: 0.000 um^2
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[INFO GPL-0018] Movable instances area: 1274.406 um^2
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[INFO GPL-0019] Utilization: 0.127 %
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[INFO GPL-0020] Standard cells area: 1274.406 um^2
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[INFO GPL-0021] Large instances area: 0.000 um^2
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[InitialPlace] Iter: 1 conjugate gradient residual: 0.00186203 HPWL: 3046720
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[InitialPlace] Iter: 2 conjugate gradient residual: 0.00000010 HPWL: 125934
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[InitialPlace] Iter: 3 conjugate gradient residual: 0.00000010 HPWL: 61934
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[InitialPlace] Iter: 4 conjugate gradient residual: 0.00000008 HPWL: 61920
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[InitialPlace] Iter: 5 conjugate gradient residual: 0.00000009 HPWL: 61936
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Placement Analysis
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---------------------------------
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total displacement 6902.2 u
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average displacement 24.4 u
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max displacement 36.1 u
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original HPWL 0.0 u
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legalized HPWL 454.9 u
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delta HPWL 1977770 %
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[INFO CTS-0050] Root buffer is CLKBUF_X3.
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[INFO CTS-0051] Sink buffer is CLKBUF_X3.
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[INFO CTS-0052] The following clock buffers will be used for CTS:
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CLKBUF_X3
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[INFO CTS-0049] Characterization buffer is CLKBUF_X3.
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[INFO CTS-0007] Net "clk" found for clock "core".
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[INFO CTS-0010] Clock net "clk" has 4 sinks.
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[INFO CTS-0010] Clock net "hi_gclk2" has 36 sinks.
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[INFO CTS-0010] Clock net "hi_gclk5" has 134 sinks.
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[INFO CTS-0011] Clock net "gclk4" for macros has 1 sinks.
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[INFO CTS-0011] Clock net "gclk4_regs" for registers has 36 sinks.
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[INFO CTS-0010] Clock net "gclk3" has 36 sinks.
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[INFO CTS-0010] Clock net "gclk1" has 36 sinks.
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[INFO CTS-0008] TritonCTS found 7 clock nets.
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[INFO CTS-0097] Characterization used 1 buffer(s) types.
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[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
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[INFO CTS-0027] Generating H-Tree topology for net clk.
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[INFO CTS-0028] Total number of sinks: 4.
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[INFO CTS-0090] Sinks will be clustered based on buffer max cap.
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[INFO CTS-0030] Number of static layers: 1.
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[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
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[INFO CTS-0021] Distance between buffers: 7 units (100 um).
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[INFO CTS-0023] Original sink region: [(946595, 1947820), (983835, 1983380)].
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[INFO CTS-0024] Normalized sink region: [(67.6139, 139.13), (70.2739, 141.67)].
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[INFO CTS-0025] Width: 2.6600.
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[INFO CTS-0026] Height: 2.5400.
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Level 1
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Direction: Horizontal
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Sinks per sub-region: 2
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Sub-region size: 1.3300 X 2.5400
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[INFO CTS-0034] Segment length (rounded): 1.
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[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
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[INFO CTS-0035] Number of sinks covered: 4.
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[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
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[INFO CTS-0027] Generating H-Tree topology for net hi_gclk2.
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[INFO CTS-0028] Total number of sinks: 36.
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[INFO CTS-0090] Sinks will be clustered based on buffer max cap.
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[INFO CTS-0030] Number of static layers: 1.
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[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
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[INFO CTS-0021] Distance between buffers: 7 units (100 um).
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[INFO CTS-0023] Original sink region: [(931950, 1930770), (1067610, 1997970)].
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[INFO CTS-0024] Normalized sink region: [(66.5679, 137.912), (76.2579, 142.712)].
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[INFO CTS-0025] Width: 9.6900.
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[INFO CTS-0026] Height: 4.8000.
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Level 1
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Direction: Horizontal
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Sinks per sub-region: 18
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Sub-region size: 4.8450 X 4.8000
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[INFO CTS-0034] Segment length (rounded): 2.
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Level 2
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Direction: Vertical
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Sinks per sub-region: 9
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Sub-region size: 4.8450 X 2.4000
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[INFO CTS-0034] Segment length (rounded): 1.
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[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
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[INFO CTS-0035] Number of sinks covered: 36.
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[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
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[INFO CTS-0027] Generating H-Tree topology for net hi_gclk5.
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[INFO CTS-0028] Total number of sinks: 134.
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[INFO CTS-0090] Sinks will be clustered based on buffer max cap.
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[INFO CTS-0030] Number of static layers: 1.
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[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
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[INFO CTS-0021] Distance between buffers: 7 units (100 um).
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[INFO CTS-0023] Original sink region: [(951330, 1947570), (1048230, 1997970)].
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[INFO CTS-0024] Normalized sink region: [(67.9521, 139.112), (74.8736, 142.712)].
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[INFO CTS-0025] Width: 6.9214.
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[INFO CTS-0026] Height: 3.6000.
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Level 1
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Direction: Horizontal
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Sinks per sub-region: 67
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Sub-region size: 3.4607 X 3.6000
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[INFO CTS-0034] Segment length (rounded): 1.
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Level 2
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Direction: Vertical
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Sinks per sub-region: 34
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Sub-region size: 3.4607 X 1.8000
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[INFO CTS-0034] Segment length (rounded): 1.
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Level 3
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Direction: Horizontal
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Sinks per sub-region: 17
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Sub-region size: 1.7304 X 1.8000
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[INFO CTS-0034] Segment length (rounded): 1.
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Level 4
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Direction: Vertical
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Sinks per sub-region: 9
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Sub-region size: 1.7304 X 0.9000
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[INFO CTS-0034] Segment length (rounded): 1.
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[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
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[INFO CTS-0035] Number of sinks covered: 134.
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[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
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[INFO CTS-0027] Generating H-Tree topology for net gclk4.
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[INFO CTS-0028] Total number of sinks: 1.
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[INFO CTS-0029] Macro sinks will be clustered in groups of up to 4 and with maximum cluster diameter of 50.0 um.
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[INFO CTS-0030] Number of static layers: 1.
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[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
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[INFO CTS-0021] Distance between buffers: 7 units (100 um).
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[INFO CTS-0023] Original sink region: [(964455, 1966580), (964455, 1966580)].
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[INFO CTS-0024] Normalized sink region: [(68.8896, 140.47), (68.8896, 140.47)].
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[INFO CTS-0025] Width: 0.0000.
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[INFO CTS-0026] Height: 0.0000.
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Level 1
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Direction: Vertical
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Sinks per sub-region: 1
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Sub-region size: 0.0000 X 0.0000
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[INFO CTS-0034] Segment length (rounded): 1.
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[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
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[INFO CTS-0035] Number of sinks covered: 1.
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[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
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[INFO CTS-0027] Generating H-Tree topology for net gclk4_regs.
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[INFO CTS-0028] Total number of sinks: 36.
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[INFO CTS-0090] Sinks will be clustered based on buffer max cap.
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[INFO CTS-0030] Number of static layers: 1.
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[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
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[INFO CTS-0021] Distance between buffers: 7 units (100 um).
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[INFO CTS-0023] Original sink region: [(944870, 1938830), (1054690, 1997970)].
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[INFO CTS-0024] Normalized sink region: [(67.4907, 138.488), (75.335, 142.712)].
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[INFO CTS-0025] Width: 7.8443.
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[INFO CTS-0026] Height: 4.2243.
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Level 1
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Direction: Horizontal
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Sinks per sub-region: 18
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Sub-region size: 3.9221 X 4.2243
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[INFO CTS-0034] Segment length (rounded): 2.
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Level 2
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Direction: Vertical
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Sinks per sub-region: 9
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Sub-region size: 3.9221 X 2.1121
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[INFO CTS-0034] Segment length (rounded): 1.
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[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
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[INFO CTS-0035] Number of sinks covered: 36.
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[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
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[INFO CTS-0027] Generating H-Tree topology for net gclk3.
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[INFO CTS-0028] Total number of sinks: 36.
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[INFO CTS-0090] Sinks will be clustered based on buffer max cap.
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[INFO CTS-0030] Number of static layers: 1.
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[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
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[INFO CTS-0021] Distance between buffers: 7 units (100 um).
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[INFO CTS-0023] Original sink region: [(983630, 1975570), (1022390, 1997970)].
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[INFO CTS-0024] Normalized sink region: [(70.2593, 141.112), (73.0279, 142.712)].
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[INFO CTS-0025] Width: 2.7686.
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[INFO CTS-0026] Height: 1.6000.
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Level 1
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Direction: Horizontal
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Sinks per sub-region: 18
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Sub-region size: 1.3843 X 1.6000
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[INFO CTS-0034] Segment length (rounded): 1.
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Level 2
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Direction: Vertical
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Sinks per sub-region: 9
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Sub-region size: 1.3843 X 0.8000
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[INFO CTS-0034] Segment length (rounded): 1.
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[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
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[INFO CTS-0035] Number of sinks covered: 36.
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[INFO CTS-0201] 0 blockages from hard placement blockages and placed macros will be used.
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[INFO CTS-0027] Generating H-Tree topology for net gclk1.
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[INFO CTS-0028] Total number of sinks: 36.
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[INFO CTS-0090] Sinks will be clustered based on buffer max cap.
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[INFO CTS-0030] Number of static layers: 1.
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[INFO CTS-0020] Wire segment unit: 14000 dbu (7 um).
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[INFO CTS-0021] Distance between buffers: 7 units (100 um).
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[INFO CTS-0023] Original sink region: [(938410, 1933230), (1061150, 1997970)].
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[INFO CTS-0024] Normalized sink region: [(67.0293, 138.088), (75.7964, 142.712)].
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[INFO CTS-0025] Width: 8.7671.
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[INFO CTS-0026] Height: 4.6243.
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Level 1
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Direction: Horizontal
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Sinks per sub-region: 18
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Sub-region size: 4.3836 X 4.6243
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[INFO CTS-0034] Segment length (rounded): 2.
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Level 2
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Direction: Vertical
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Sinks per sub-region: 9
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Sub-region size: 4.3836 X 2.3121
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[INFO CTS-0034] Segment length (rounded): 1.
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[INFO CTS-0032] Stop criterion found. Max number of sinks is 15.
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[INFO CTS-0035] Number of sinks covered: 36.
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[INFO CTS-0018] Created 3 clock buffers.
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[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
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[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
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[INFO CTS-0015] Created 3 clock nets.
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[INFO CTS-0016] Fanout distribution for the current clock = 2:2..
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[INFO CTS-0017] Max level of the clock tree: 1.
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[INFO CTS-0018] Created 5 clock buffers.
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[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
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[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
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[INFO CTS-0015] Created 5 clock nets.
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[INFO CTS-0016] Fanout distribution for the current clock = 8:3, 12:1..
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[INFO CTS-0017] Max level of the clock tree: 2.
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[INFO CTS-0018] Created 17 clock buffers.
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[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
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[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
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[INFO CTS-0015] Created 17 clock nets.
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[INFO CTS-0016] Fanout distribution for the current clock = 5:1, 6:3, 7:3, 8:3, 9:1, 10:1, 11:2, 12:1, 13:1..
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[INFO CTS-0017] Max level of the clock tree: 4.
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[INFO CTS-0018] Created 2 clock buffers.
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[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
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[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
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[INFO CTS-0015] Created 2 clock nets.
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[INFO CTS-0016] Fanout distribution for the current clock = 1:1..
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[INFO CTS-0017] Max level of the clock tree: 1.
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[INFO CTS-0018] Created 5 clock buffers.
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[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
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[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
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[INFO CTS-0015] Created 5 clock nets.
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[INFO CTS-0016] Fanout distribution for the current clock = 8:2, 10:2..
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[INFO CTS-0017] Max level of the clock tree: 2.
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[INFO CTS-0018] Created 5 clock buffers.
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[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
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[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
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[INFO CTS-0015] Created 5 clock nets.
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[INFO CTS-0016] Fanout distribution for the current clock = 6:1, 9:2, 12:1..
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[INFO CTS-0017] Max level of the clock tree: 2.
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[INFO CTS-0018] Created 5 clock buffers.
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[INFO CTS-0012] Minimum number of buffers in the clock path: 2.
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[INFO CTS-0013] Maximum number of buffers in the clock path: 2.
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[INFO CTS-0015] Created 5 clock nets.
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[INFO CTS-0016] Fanout distribution for the current clock = 7:1, 9:1, 10:2..
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[INFO CTS-0017] Max level of the clock tree: 2.
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[INFO CTS-0098] Clock net "clk"
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[INFO CTS-0099] Sinks 4
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[INFO CTS-0100] Leaf buffers 0
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[INFO CTS-0101] Average sink wire length 51.45 um
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[INFO CTS-0102] Path depth 2 - 2
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[INFO CTS-0207] Leaf load cells 25
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[INFO CTS-0098] Clock net "hi_gclk2"
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[INFO CTS-0099] Sinks 39
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[INFO CTS-0100] Leaf buffers 0
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[INFO CTS-0101] Average sink wire length 54.07 um
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[INFO CTS-0102] Path depth 2 - 2
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[INFO CTS-0207] Leaf load cells 25
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[INFO CTS-0098] Clock net "hi_gclk5"
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[INFO CTS-0099] Sinks 149
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[INFO CTS-0100] Leaf buffers 0
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[INFO CTS-0101] Average sink wire length 45.09 um
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[INFO CTS-0102] Path depth 2 - 2
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[INFO CTS-0207] Leaf load cells 25
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[INFO CTS-0124] Clock net "gclk4"
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[INFO CTS-0125] Sinks 1
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[INFO CTS-0098] Clock net "gclk4_regs"
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[INFO CTS-0099] Sinks 38
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[INFO CTS-0100] Leaf buffers 0
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[INFO CTS-0101] Average sink wire length 26.61 um
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[INFO CTS-0102] Path depth 2 - 2
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[INFO CTS-0207] Leaf load cells 25
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[INFO CTS-0098] Clock net "gclk3"
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[INFO CTS-0099] Sinks 39
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[INFO CTS-0100] Leaf buffers 0
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[INFO CTS-0101] Average sink wire length 40.27 um
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[INFO CTS-0102] Path depth 2 - 2
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[INFO CTS-0207] Leaf load cells 25
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[INFO CTS-0098] Clock net "gclk1"
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[INFO CTS-0099] Sinks 38
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[INFO CTS-0100] Leaf buffers 0
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[INFO CTS-0101] Average sink wire length 62.29 um
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[INFO CTS-0102] Path depth 2 - 2
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[INFO CTS-0207] Leaf load cells 25
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[INFO CTS-0033] Balancing latency for clock core
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[DEBUG CTS-insertion delay] new delay buffer delaybuf_0_core is inserted at (989233 1955088)
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[DEBUG CTS-insertion delay] new delay buffer delaybuf_1_core is inserted at (994631 1962356)
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[DEBUG CTS-insertion delay] new delay buffer delaybuf_2_core is inserted at (974097 1968163)
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[DEBUG CTS-insertion delay] new delay buffer delaybuf_3_core is inserted at (968729 1969502)
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[DEBUG CTS-insertion delay] new delay buffer delaybuf_4_core is inserted at (963362 1970841)
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[DEBUG CTS-insertion delay] new delay buffer delaybuf_5_core is inserted at (949030 1975102)
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[DEBUG CTS-insertion delay] new delay buffer delaybuf_6_core is inserted at (960798 1966825)
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[DEBUG CTS-insertion delay] new delay buffer delaybuf_7_core is inserted at (956131 1966825)
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[INFO CTS-0036] inserted 8 delay buffers
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[INFO CTS-0037] Total number of delay buffers: 8
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No differences found.
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No differences found.

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