rsz: Used make_result_file proc in the new regressions.

Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>

Author: jhkim-pii

src/rsz/test/rebuffer1.tcl

@@ -33,10 +33,12 @@ report_tns -digits 3
 rsz::fully_rebuffer [get_pins u_mid1/u_leaf2/dff2/Q]
 
 # generate .v and .def files
-set rebuffered_verilog_filename "rebuffer1_out.v"
+set verilog_filename "rebuffer1_out.v"
+set rebuffered_verilog_filename [make_result_file $verilog_filename]
 write_verilog $rebuffered_verilog_filename
-diff_file ${rebuffered_verilog_filename}ok $rebuffered_verilog_filename
+diff_file ${verilog_filename}ok $rebuffered_verilog_filename
 
-set rebuffered_def_filename "rebuffer1_out.def"
+set def_filename "rebuffer1_out.def"
+set rebuffered_def_filename [make_result_file $def_filename]
 write_def $rebuffered_def_filename
-diff_file ${rebuffered_def_filename}ok $rebuffered_def_filename
+diff_file ${def_filename}ok $rebuffered_def_filename

src/rsz/test/rebuffer1_hier.tcl

@@ -27,13 +27,15 @@ report_tns -digits 3
 rsz::fully_rebuffer [get_pins u_mid1/u_leaf2/dff2/Q]
 
 # generate .v and .def files
-set rebuffered_verilog_filename "rebuffer1_hier_out.v"
+set verilog_filename "rebuffer1_hier_out.v"
+set rebuffered_verilog_filename [make_result_file $verilog_filename]
 write_verilog $rebuffered_verilog_filename
-diff_file ${rebuffered_verilog_filename}ok $rebuffered_verilog_filename
+diff_file ${verilog_filename}ok $rebuffered_verilog_filename
 
-set rebuffered_def_filename "rebuffer1_hier_out.def"
+set def_filename "rebuffer1_hier_out.def"
+set rebuffered_def_filename [make_result_file $def_filename]
 write_def $rebuffered_def_filename
-diff_file ${rebuffered_def_filename}ok $rebuffered_def_filename
+diff_file $def_filename}ok $rebuffered_def_filename
 
 # TODO: there is an issue that the name name (\u_mid1/l2_out1) of
 #       the new buffer input u_mid1/u_leaf2/rebuffer1/A is wrong

src/rsz/test/repair_setup9.tcl

@@ -34,10 +34,12 @@ repair_timing -setup -skip_last_gasp -skip_pin_swap -skip_gate_cloning \
   -skip_buffer_removal -max_passes 10
 
 # generate .v and .def files
-set repaired_verilog_filename "repair_setup9_out.v"
+set verilog_filename "repair_setup9_out.v"
+set repaired_verilog_filename [make_result_file $verilog_filename]
 write_verilog $repaired_verilog_filename
-diff_file ${repaired_verilog_filename}ok $repaired_verilog_filename
+diff_file ${verilog_filename}ok $repaired_verilog_filename
 
-set repaired_def_filename "repair_setup9_out.def"
+set def_filename "repair_setup9_out.def"
+set repaired_def_filename [make_result_file $def_filename]
 write_def $repaired_def_filename
-diff_file ${repaired_def_filename}ok $repaired_def_filename
+diff_file ${def_filename}ok $repaired_def_filename

src/rsz/test/repair_setup9_hier.tcl

@@ -34,13 +34,15 @@ repair_timing -setup -skip_last_gasp -skip_pin_swap -skip_gate_cloning \
   -skip_buffer_removal -max_passes 10
 
 # generate .v and .def files
-set repaired_verilog_filename "repair_setup9_hier_out.v"
+set verilog_filename "repair_setup9_hier_out.v"
+set repaired_verilog_filename [make_result_file $verilog_filename]
 write_verilog $repaired_verilog_filename
-diff_file ${repaired_verilog_filename}ok $repaired_verilog_filename
+diff_file ${verilog_filename}ok $repaired_verilog_filename
 
-set repaired_def_filename "repair_setup9_hier_out.def"
+set def_filename "repair_setup9_hier_out.def"
+set repaired_def_filename [make_result_file $def_filename]
 write_def $repaired_def_filename
-diff_file ${repaired_def_filename}ok $repaired_def_filename
+diff_file ${def_filename}ok $repaired_def_filename
 
 # TODO: there is an issue that the name name (\u_mid1/l2_out1) of
 #       the new buffer input u_mid1/u_leaf2/rebuffer1/A is wrong