@@ -438,6 +438,7 @@ void Verilog2db::makeModBTerms(Cell* cell, dbModule* module)
438438 std::unique_ptr<CellPortIterator> cp_iter{network_->portIterator (cell)};
439439 while (cp_iter->hasNext ()) {
440440 Port* port = cp_iter->next ();
441+ const dbIoType io_type = staToDb (network_->direction (port));
441442 if (network_->isBus (port)) {
442443 // make the bus port as part of the port set for the cell.
443444 const char * port_name = network_->name (port);
@@ -447,7 +448,6 @@ void Verilog2db::makeModBTerms(Cell* cell, dbModule* module)
447448 network_->fromIndex (port),
448449 network_->toIndex (port));
449450 bmodterm->setBusPort (dbbusport);
450- const dbIoType io_type = staToDb (network_->direction (port));
451451 bmodterm->setIoType (io_type);
452452
453453 //
@@ -475,12 +475,11 @@ void Verilog2db::makeModBTerms(Cell* cell, dbModule* module)
475475 dbbusport->setLast (modbterm);
476476 }
477477 dbIoType io_type = staToDb (network_->direction (port));
478- bmodterm ->setIoType (io_type);
478+ modbterm ->setIoType (io_type);
479479 }
480480 } else {
481481 const std::string port_name = network_->name (port);
482482 dbModBTerm* bmodterm = dbModBTerm::create (module , port_name.c_str ());
483- const dbIoType io_type = staToDb (network_->direction (port));
484483 bmodterm->setIoType (io_type);
485484 debugPrint (logger_,
486485 utl::ODB,
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