minor typo fixes

Author: dreamos82

04_Memory_Management/03_Paging.md

@@ -179,29 +179,29 @@ Note about PWT and PCD, the definiton of those bits depends on whether PAT (page
 
 If we are using 2MB pages this is how the address will be handled by the paging mechanism:
 
-|            |           |                     |            |              |
-|------------|-----------|---------------------|------------|--------------|
-| 63 .... 48 | 47 ... 39 | 38   ... 32  31  30 | 29  ..  21 | 20 19 ...  0 |
-|  1 ...  1  | 1  ...  1 | 1    ... 1   1   0  | 0   ... 0  | 0  0  ...  0 |
-|  Sgn. ext  |    PML4   |      PDPR           |   Page dir |    Offset    |
+|            |           |               |            |           |
+|------------|-----------|---------------|------------|-----------|
+| 63 .... 48 | 47 ... 39 | 38   ...   30 | 29  ..  21 | 20 ...  0 |
+|  1 ...  1  | 1  ...  1 | 1    ...    0 | 0   ... 0  | 0  ...  0 |
+|  Sgn. ext  |    PML4   |      PDPR     |   Page dir |   Offset  |
 
 * Bits 63 to 48, not used in address translation.
 * Bits 47 ... 39 are the PML4 entry.
 * Bits 38 ... 30 are the PDPR entry.
 * Bits 29 ... 21 are the PD entry.
 * Offset in the page directory.
 
-Every table has 512 elements, so we have an address space of $2^{512} * 2^{512} * 2^{512} * 0x200000$ (that is the page size)
+Every table has 512 elements, so we have an address space of $2^{512}*2^{512}*2^{512}*0x200000$ (that is the page size)
 
 ### Address translation Using 4KB Pages
 
 If we are using 4kB pages this is how the address will be handled by the paging mechanism:
 
-|            |           |                     |            |             |              |
-|------------|-----------|---------------------|------------|-------------|--------------|
-| 63 .... 48 | 47 ... 39 | 38   ... 32  31  30 | 29  ..  21 | 20  ...  12 | 11 10 ...  0 |
-| 1   ...  1 | 1  ...  1 | 1    ... 1   1   0  | 0   ... 0  | 0   ...  0  | 0 ...  ... 0 |
-|  Sgn. ext  |    PML4   |      PDPR           |   Page dir |  Page Table |   Offset     |
+|           |           |           |           |             |           |
+|-----------|-----------|-----------|-----------|-------------|-----------|
+| 63 ... 48 | 47 ... 39 | 38 ... 30 | 29 ... 21 | 20  ...  12 | 11 ...  0 |
+| 1  ...  1 | 1  ...  1 | 1  ... 0  | 0  ... 0  | 0   ...  0  | 0  ... 0  |
+|  Sgn. ext |    PML4   |   PDPR    |  Page dir |  Page Table |   Offset  |
 
 * Bits 63 to 48, not used in address translation.
 * Bits 47 ... 39 are the PML4 entry.
@@ -211,7 +211,7 @@ If we are using 4kB pages this is how the address will be handled by the paging
 * Offset in the page table.
 
 Same as above: 
-Every table has 512 elements, so we have an address space of: $2^{512} * 2^{512} * 2^{512} * 2^{512} * 0x1000$ (that is the page size)
+Every table has 512 elements, so we have an address space of: $2^{512}*2^{512}*2^{512}*2^{512}*0x1000$ (that is the page size)
 
 ## Page Fault
 
@@ -248,6 +248,6 @@ A few examples of recursive addresses:
 
 * PML4: 511 (hex: 1ff) - PDPR: 510 (hex: 1fe) - PD 0 (hex: 0) using 2mb pages translates to: `0xFFFF'FFFF'8000'0000`.
 * Let's assume we mapped PML4 into itself at entry 510, 
-    - If we want to access the content of the PML4 page itself, using the recursion we need to build a special address using the entries: PML4: 510, PDPR: 510, PD: 510, PT: 510, now keep in mind that the 510th entry of PML4 is PML4 itself, so this means that when the processor loads that entry, it loads PML4 itself instead of PDPR, but now the value for the PDPR entry is still 510, that is still PML4 then, the table loaded is PML4 again, repat this process for PD and PT wit page number equals to 510, and we obtain access to the PML4 page itself.
-    - Now using a similar approach we can get acces to other tables, for example the following values: PML4: 510, PDPR:510, PD: 1, PT: 256, will give access at the Page Directory PD at  entry number 256 in PDPR that is  contained in the first PML4 entry .
+    - If we want to access the content of the PML4 page itself, using the recursion we need to build a special address using the entries: _PML4: 510, PDPR: 510, PD: 510, PT: 510_, now keep in mind that the 510th entry of PML4 is PML4 itself, so this means that when the processor loads that entry, it loads PML4 itself instead of PDPR, but now the value for the PDPR entry is still 510, that is still PML4 then, the table loaded is PML4 again, repat this process for PD and PT with page number equals to 510, and we got access to the PML4 table.
+    - Now using a similar approach we can get acces to other tables, for example the following values: _PML4: 510, PDPR:510, PD: 1, PT: 256_, will give access at the Page Directory PD at entry number 256 in PDPR that is contained in the first PML4 entry.
 

05_Scheduling/04_Locks.md

@@ -42,13 +42,14 @@ void thead_two() {
 }
 ```
 
-What would we expect to see on the serial output? We don't know! It's essentially non-deterministic, since we can't know how these will be scheduled. Each thread may get to write the full string before the other is scheduled, but more like they will get in the way of each other.
-
+What would we expect to see on the serial output? We don't know! It's essentially non-deterministic, since we can't know how these will be scheduled. Each thread may get to write the full string before the other is scheduled, but more likely they will get in the way of each other.
+ 
 ![Tasks execution sequence](/Images/taskssequence.png)
 
-One example of what we could see is `Iwh aI ammi  lethe secfionrsd t stristngring`. This contains all the right characters but it's completely unreadable. The image below shows what could happen:
+The image above is an example of threads being scheduled, assuming there are only three of them in the system (labeled as _A, B, C_. 
+Imagine that A is `thread_one` and B is `thread_two`, while C does not interact with the serial. One example of what we could see then is `Iwh aI ammi  lethe secfionrsd t stristngring`. This contains all the right characters but it's completely unreadable. The image below shows what could happen:
 
-![Shared Resource Sequence](Images/sharedressequence.png)
+![Shared Resource Sequence](/Images/sharedressequence.png)
 
 What we'd expect to see is one of two outcomes: `I am the first string while I am the second` or `while I am the second I am the first string`.
 

09_Loading_Elf/03_Loading_And_Running.md

@@ -8,7 +8,7 @@ For a program to be compatible with our loader:
 - All libraries must be statically linked, we won't support dynamic linking for now. This feature isn't too hard to implement, but we will leave this as an exercise to the reader.
 - The program must be freestanding! As of right now we don't have a libc that targets our kernel. It can be worth porting (or writing) a libc later on.
 
-# Steps Required
+## Steps Required
 
 In the previous chapter we looked at the details of loading program headers, but we glossed over a lot of the high level details of loading a program. Assuming we want to start running a new program (we're ignoring `fork()` and `exec()` for the moment), we'll need to do a few things. Most of this was covered in previous chapters, and now it's a matter of putting it all together.