Fixes to user space chapters

Author: dreamos82

06_Userspace/02_Switching_Modes.md

@@ -18,7 +18,7 @@ Changing the flags atomically like this means we can go from having interrupts d
 
 ### What to Push Onto The Stack
 
-Now let's talk about what these values should be. `rflags` is an easy one: set it to `0x202`. Bit 1 is a legacy feature and must always be set, the ninth bit (`0x200`) is the `IF` interrupt enable flag. This means all other flags are cleared, and is what C/C++ and other languages expect flags to look like when starting a program.
+Now let's talk about what these values should be: `rflags` is an easy one, set it to `0x202`. Bit 1 is a legacy feature and must always be set, the ninth bit (`0x200`) is the `IF` interrupt enable flag. This means all other flags are cleared, and is what C/C++ and other languages expect flags to look like when starting a program.
 
 For `ss` and `cs` it depends on the layout of your GDT. We'll assume that there are 5 entries in the GDT:
 
@@ -28,7 +28,7 @@ For `ss` and `cs` it depends on the layout of your GDT. We'll assume that there
 - 0x18, User Code (ring 3)
 - 0x20, User Data (ring 3)
 
-Now `ss` and `cs` are *selectors*, which you'll remember are not just a byte offset into the gdt, but the lowest two bits contain a field called _RPL_ (Requested Privilege Level) is a legacy feature, but it's still enforced by the cpu, so we have to use it. RPL is a sort of 'override' for the target ring, it's useful in some edge cases, but otherwise is best set to the ring we want to jump to.
+Now `ss` and `cs` are *selectors*, which you'll remember are not just a byte offset into the gdt, the lowest two bits contain a field called _RPL_ (Requested Privilege Level) that is a legacy feature, but it's still enforced by the cpu, so we have to use it. _RPL_  is a sort of 'override' for the target ring, it's useful in some edge cases, but otherwise is best set to the ring we want to jump to.
 
 So if we're going to ring 0 (supervisor), RPL can be left at 0. If going to ring 3 (user) we'd set it to 3.
 

06_Userspace/03_Handling_Interrupts.md

@@ -54,14 +54,17 @@ The GDT descriptor we're going to create is a *system descriptor* (as opposed to
 The layout of the TSS system descriptor is broken down below in the following table:
 
 | Bits  | Should Be Set To | Description                         |
-|-------|------------------|-------------------------------------|
-| 15:0  | 0xFFFF           | Represents the limit field for this segment. Ignored in long mode, but best set to max value in case we support compatibility mode in the future. |
+|--------|------------------|-------------------------------------|
+| 15:0   | 0xFFFF           | Represents the limit field for this segment. Ignored in long mode, but best set to max value in case we support compatibility mode in the future. |
 | 31:16 | TSS address bits 15:0 | Contains the lowest 16 bits of the tss address. |
-| 39:32 | TSS address bits 23:16 | Contains the next 8 bits of the tss address. |
-| 47:40 | 0b10001001 | Sets the type of GDT descriptor, this magic value indicates it's a valid TSS descriptor. If curious as to how this value was created, see the manual or the section on the GDT. |
-| 55:48 | 0b10000 | Additional fields for the TSS entry. This bit means the TSS is `available`, it's generally unused in long mode, but has some side effects if compatibility mode is enabled. |
-| 63:56 | TSS address bits 31:24 | Contains the next 8 bits of the tss address. |
-| 95:64 | TSS address bits 63:32 | Contains the upper 32 bits of the tss address. |
+| 39:32  | TSS address bits 23:16 | Contains the next 8 bits of the tss address. |
+| 47:40  | 0b10001001 | Sets the type of GDT descriptor, it's DPL (bits 45:46) to 0, marks it as present (bit 47). The rest of this magic value indicates it's a valid TSS descriptor. If curious as to how this value was created, see the  manual or our section about the GDT.|
+| 55:48  | 0b10000 | Additional fields for the TSS entry. This bit means the TSS is `available`, it's generally unused in long mode, but has some side effects if compatibility mode is enabled. |
+| 63:56  | TSS address bits 31:24 | Contains the next 8 bits of the tss address. |
+| 95:64  | TSS address bits 63:32 | Contains the upper 32 bits of the tss address. |
+| 96:127 | Reserved | They should be left as 0. |
+
+Yes, it's right a TSS descriptor for the GDT is 128 bits. This because we need to specify the 64 bit address containing the TSS data structure.
 
 Now for the third step, we need to load the task register. This is similar to the segment registers, in that it has visible and invisible parts. It's loaded in a similar manner, although we use a dedicated instruction instead of a simple `mov`.
 

99_Appendices/J_Updates.md

@@ -24,3 +24,4 @@ Second book release.
 * Add paragraph about lockfree queues in IPC chapter
 * Add more details in the VMM Section of _Process and Threads_ chapter
 * Explain content of Segment Selectors in GDT chapter
+* Improve readability of some parts inside Userspace chapters