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1 parent 0b5b096 commit d9bd396Copy full SHA for d9bd396
1 file changed
src/lib.rs
@@ -345,7 +345,8 @@ fn build_isa(sess: &Session, jit: bool) -> Arc<dyn TargetIsa + 'static> {
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if target_triple.architecture == target_lexicon::Architecture::X86_64 {
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// Only set the target cpu on x86_64 as Cranelift is missing
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// the target cpu list for most other targets.
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- builder.enable(sess.target.cpu.as_ref()).unwrap();
+ // FIXME remove the replace once bytecodealliance/wasmtime#12792 lands
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+ builder.enable(&sess.target.cpu.replace("-", "_")).unwrap();
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}
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builder
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