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added IDCT rvv code from Andes#2

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ttwuAlain wants to merge 1 commit intoISRC-CAS:riscv-devfrom
ttwuAlain:andes-pr/idct
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added IDCT rvv code from Andes#2
ttwuAlain wants to merge 1 commit intoISRC-CAS:riscv-devfrom
ttwuAlain:andes-pr/idct

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@ttwuAlain
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We have created a folder under simd directory and added the code and ported IDCT functions that could gain performance on Andes RISC-V platofm.

@ttwuAlain
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tested on 40MHZ FPGA

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@BHbean
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BHbean commented Feb 27, 2024

Sorry for the late reply! I just came back work recently.

I noticed that the jidctfst-rvv and jidctint-rvv have been re-implemented. Are these implementations better than the original ones in all cases? Can you provide more test cases on some other devices with different images?

In addition, what is jidctred-rvv used for? I did not see any similar implementation in other SIMD algorithms so I'm not clear about it.

Thanks again for your continuous contributing! :)

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2 participants