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Pull requests: llvm/circt

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Pull requests list

[docs] Clarifications on AI Tool Use
#10240 opened Apr 16, 2026 by seldridge Member Loading…
[ImportVerilog] Add support for pullup/pulldown primitives
#10239 opened Apr 16, 2026 by TaoBi22 Contributor Loading…
1
[circt-verilog] Add -Xslang passthrough flag for Slang frontend.
#10238 opened Apr 16, 2026 by jpienaar Member Loading…
Plumb dbg.variable anchors into SMT symbol names
#10237 opened Apr 16, 2026 by 5iri Contributor Loading…
1
Add union roundtrip
#10236 opened Apr 16, 2026 by jpienaar Member Loading…
ImportVerilog: fix signedness propagation in ConversionExpression lowering
#10235 opened Apr 16, 2026 by kaituo-crypto Loading…
[Synth] Add synth.xor_inv
#10233 opened Apr 16, 2026 by uenoku Member Loading…
2
[github] Add a PR template for AI policy
#10231 opened Apr 16, 2026 by uenoku Member Loading…
1
[Synth] Make FunctionalReduction runnable on any op
#10230 opened Apr 15, 2026 by SmitVaishnav Contributor Loading…
3
[FIRRTL][LowerLayers] Add probe type support
#10223 opened Apr 15, 2026 by prithayan Contributor Loading…
1
[Sim] Add cascade erase for print/proc.print format/get_file producer chains
#10204 opened Apr 14, 2026 by nanjo712 Contributor Loading…
4
[FIRRTL] InferDomains: drive undriven domain wires
#10197 opened Apr 13, 2026 by rwy7 Contributor Loading…
2
[Synth][CutRewriter] Add timing-preserving area-flow reselection
#10193 opened Apr 13, 2026 by uenoku Member Loading…
5
[SSP] Reimplement auxiliary dependences without symbols
#10189 opened Apr 12, 2026 by jopperm Contributor Loading…
1
don't emit redundant write_en = 0 for seq_mem
#10174 opened Apr 10, 2026 by Abhilekhgautam Loading…
1
2
DRAFT: [3/2] [Moore] Lower class object access and virtual dispatch through LLVM memory
#10166 opened Apr 9, 2026 by Scheremo Contributor • Draft
[FIRRTL] Add lower-to-core lowering mode
#10162 opened Apr 9, 2026 by uenoku Member • Draft
13
[FIRRTL][SpecializeOption] Allow specialization of non-existent option
#10158 opened Apr 8, 2026 by uenoku Member Loading…
1
[Moore][ImportVerilog] Implement static $cast via materializeConversion ImportVerilog
#10156 opened Apr 8, 2026 by sunhailong2001 Contributor Loading…
14
[FIRRTLToHW] Lower FIRRTL prints to Sim
#10153 opened Apr 8, 2026 by nanjo712 Contributor Loading…
2
[FIRRTLToHW] Lower firrtl.attach to new hw.attach and migrate SV-specific lowering logic to HWToSV.
#10138 opened Apr 6, 2026 by nanjo712 Contributor Loading…
6
[Synth][FunctionalReduction] Fix a SSA cycle
#10137 opened Apr 6, 2026 by uenoku Member Loading…
1
1
[FIRRTL] Fix getBitWidth to handle AnalogType
#10136 opened Apr 6, 2026 by unlsycn Member Loading…
[2/2] [MooreToCore] Lower vtable method loads and vptr init
#10130 opened Apr 5, 2026 by Scheremo Contributor • Draft
1
[1/2] [MooreToCore] Lower symbolic vtables to LLVM globals
#10129 opened Apr 5, 2026 by Scheremo Contributor • Draft
10
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