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Merge branches 'clk-visconti', 'clk-imx', 'clk-microchip', 'clk-rockchip' and 'clk-qcom' into clk-next
* clk-visconti: clk: visconti: Add VIIF clocks dt-bindings: clock: tmpv770x: Add VIIF clocks dt-bindings: clock: tmpv770x: Remove definition of number of clocks clk: visconti: Do not define number of clocks in bindings * clk-imx: clk: imx: add driver for imx8ulp's sim lpav dt-bindings: clock: document 8ULP's SIM LPAV clk: imx: imx8mp-audiomix: use devm_auxiliary_device_create() to simple code clk: imx: Add some delay before deassert the reset * clk-microchip: reset: mpfs: add non-auxiliary bus probing clk: lan966x: remove unused dt-bindings include clk: microchip: mpfs: use regmap for clocks dt-bindings: clk: microchip: mpfs: remove first reg region * clk-rockchip: clk: rockchip: Add clock and reset driver for RK3506 dt-bindings: clock: rockchip: Add RK3506 clock and reset unit clk: rockchip: Add clock controller for the RV1126B dt-bindings: clock, reset: Add support for rv1126b clk: rockchip: Implement rockchip_clk_register_armclk_multi_pll() dt-bindings: clock: rk3568: Drop CLK_NR_CLKS define clk: rockchip: rk3568: Drop CLK_NR_CLKS usage dt-bindings: clock: rk3568: Add SCMI clock ids * clk-qcom: (48 commits) clk: qcom: Mark camcc_sm7150_hws static clk: qcom: x1e80100-dispcc: Add USB4 router link resets dt-bindings: clock: qcom: x1e80100-dispcc: Add USB4 router link resets clk: qcom: videocc-sm8750: Add video clock controller driver for SM8750 dt-bindings: clock: qcom: Add SM8750 video clock controller clk: qcom: branch: Extend invert logic for branch2 mem clocks clk: qcom: ecpricc-qdu100: Add mem_enable_mask to the clock memory branch clk: qcom: clk_mem_branch: add enable mask and invert flags clk: qcom: mmcc-sdm660: Add missing MDSS reset dt-bindings: clock: mmcc-sdm660: Add missing MDSS reset clk: qcom: use different Kconfig prompts for APSS IPQ5424/6018 drivers clk: qcom: apss-ipq5424: remove unused 'apss_clk' structure dt-bindings: clock: qcom: Add Kaanapali Global clock controller dt-bindings: clock: qcom: Document the Kaanapali TCSR Clock Controller dt-bindings: clock: qcom-rpmhcc: Add RPMHCC for Kaanapali clk: qcom: tcsrcc-glymur: Update register offsets for clock refs clk: qcom: gcc-qcs615: Update the SDCC clock to use shared_floor_ops clk: qcom: camcc-sm7150: Fix PLL config of PLL2 clk: qcom: camcc-sm6350: Fix PLL config of PLL2 clk: qcom: Add NSS clock controller driver for IPQ5424 ...
6 parents 0999df6 + b65e179 + d409f53 + b5b9e93 + 53fbbc2 + 1413717 commit 6f17217

79 files changed

Lines changed: 8298 additions & 245 deletions

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‎Documentation/devicetree/bindings/clock/fsl,imx8ulp-sim-lpav.yaml‎

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@@ -0,0 +1,72 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/clock/fsl,imx8ulp-sim-lpav.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: NXP i.MX8ULP LPAV System Integration Module (SIM)
8+
9+
maintainers:
10+
- Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
11+
12+
description:
13+
The i.MX8ULP LPAV subsystem contains a block control module known as
14+
SIM LPAV, which offers functionalities such as clock gating or reset
15+
line assertion/de-assertion.
16+
17+
properties:
18+
compatible:
19+
const: fsl,imx8ulp-sim-lpav
20+
21+
reg:
22+
maxItems: 1
23+
24+
clocks:
25+
maxItems: 3
26+
27+
clock-names:
28+
items:
29+
- const: bus
30+
- const: core
31+
- const: plat
32+
33+
'#clock-cells':
34+
const: 1
35+
36+
'#reset-cells':
37+
const: 1
38+
39+
mux-controller:
40+
$ref: /schemas/mux/reg-mux.yaml#
41+
42+
required:
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- compatible
44+
- reg
45+
- clocks
46+
- clock-names
47+
- '#clock-cells'
48+
- '#reset-cells'
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- mux-controller
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51+
additionalProperties: false
52+
53+
examples:
54+
- |
55+
#include <dt-bindings/clock/imx8ulp-clock.h>
56+
57+
clock-controller@2da50000 {
58+
compatible = "fsl,imx8ulp-sim-lpav";
59+
reg = <0x2da50000 0x10000>;
60+
clocks = <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>,
61+
<&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>,
62+
<&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>;
63+
clock-names = "bus", "core", "plat";
64+
#clock-cells = <1>;
65+
#reset-cells = <1>;
66+
67+
mux-controller {
68+
compatible = "reg-mux";
69+
#mux-control-cells = <1>;
70+
mux-reg-masks = <0x8 0x00000200>;
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};
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};

‎Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -22,16 +22,23 @@ properties:
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const: microchip,mpfs-clkcfg
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reg:
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items:
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- description: |
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clock config registers:
28-
These registers contain enable, reset & divider tables for the, cpu,
29-
axi, ahb and rtc/mtimer reference clocks as well as enable and reset
30-
for the peripheral clocks.
31-
- description: |
32-
mss pll dri registers:
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Block of registers responsible for dynamic reconfiguration of the mss
34-
pll
25+
oneOf:
26+
- items:
27+
- description: |
28+
clock config registers:
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These registers contain enable, reset & divider tables for the, cpu,
30+
axi, ahb and rtc/mtimer reference clocks as well as enable and reset
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for the peripheral clocks.
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- description: |
33+
mss pll dri registers:
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Block of registers responsible for dynamic reconfiguration of the mss
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pll
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deprecated: true
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- items:
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- description: |
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mss pll dri registers:
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Block of registers responsible for dynamic reconfiguration of the mss
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pll
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clocks:
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maxItems: 1
@@ -69,11 +76,12 @@ examples:
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- |
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#include <dt-bindings/clock/microchip,mpfs-clock.h>
7178
soc {
72-
#address-cells = <2>;
73-
#size-cells = <2>;
74-
clkcfg: clock-controller@20002000 {
79+
#address-cells = <1>;
80+
#size-cells = <1>;
81+
82+
clkcfg: clock-controller@3E001000 {
7583
compatible = "microchip,mpfs-clkcfg";
76-
reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
84+
reg = <0x3E001000 0x1000>;
7785
clocks = <&ref>;
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#clock-cells = <1>;
7987
};

‎Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -4,29 +4,37 @@
44
$id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
55
$schema: http://devicetree.org/meta-schemas/core.yaml#
66

7-
title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574
7+
title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 and IPQ5424
88

99
maintainers:
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- Bjorn Andersson <andersson@kernel.org>
1111
- Anusha Rao <quic_anusha@quicinc.com>
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1313
description: |
1414
Qualcomm networking sub system clock control module provides the clocks,
15-
resets on IPQ9574
15+
resets on IPQ9574 and IPQ5424
1616
17-
See also::
17+
See also:
18+
include/dt-bindings/clock/qcom,ipq5424-nsscc.h
1819
include/dt-bindings/clock/qcom,ipq9574-nsscc.h
20+
include/dt-bindings/reset/qcom,ipq5424-nsscc.h
1921
include/dt-bindings/reset/qcom,ipq9574-nsscc.h
2022
2123
properties:
2224
compatible:
23-
const: qcom,ipq9574-nsscc
25+
enum:
26+
- qcom,ipq5424-nsscc
27+
- qcom,ipq9574-nsscc
2428

2529
clocks:
2630
items:
2731
- description: Board XO source
28-
- description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source
29-
- description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source
32+
- description: CMN_PLL NSS (Bias PLL cc) clock source. This clock rate
33+
can vary for different IPQ SoCs. For example, it is 1200 MHz on the
34+
IPQ9574 and 300 MHz on the IPQ5424.
35+
- description: CMN_PLL PPE (Bias PLL ubi nc) clock source. The clock
36+
rate can vary for different IPQ SoCs. For example, it is 353 MHz
37+
on the IPQ9574 and 375 MHz on the IPQ5424.
3038
- description: GCC GPLL0 OUT AUX clock source
3139
- description: Uniphy0 NSS Rx clock source
3240
- description: Uniphy0 NSS Tx clock source
@@ -42,8 +50,12 @@ properties:
4250
clock-names:
4351
items:
4452
- const: xo
45-
- const: nss_1200
46-
- const: ppe_353
53+
- enum:
54+
- nss_1200
55+
- nss
56+
- enum:
57+
- ppe_353
58+
- ppe
4759
- const: gpll0_out
4860
- const: uniphy0_rx
4961
- const: uniphy0_tx
@@ -60,6 +72,40 @@ required:
6072

6173
allOf:
6274
- $ref: qcom,gcc.yaml#
75+
- if:
76+
properties:
77+
compatible:
78+
const: qcom,ipq9574-nsscc
79+
then:
80+
properties:
81+
clock-names:
82+
items:
83+
- const: xo
84+
- const: nss_1200
85+
- const: ppe_353
86+
- const: gpll0_out
87+
- const: uniphy0_rx
88+
- const: uniphy0_tx
89+
- const: uniphy1_rx
90+
- const: uniphy1_tx
91+
- const: uniphy2_rx
92+
- const: uniphy2_tx
93+
- const: bus
94+
else:
95+
properties:
96+
clock-names:
97+
items:
98+
- const: xo
99+
- const: nss
100+
- const: ppe
101+
- const: gpll0_out
102+
- const: uniphy0_rx
103+
- const: uniphy0_tx
104+
- const: uniphy1_rx
105+
- const: uniphy1_tx
106+
- const: uniphy2_rx
107+
- const: uniphy2_tx
108+
- const: bus
63109

64110
unevaluatedProperties: false
65111

@@ -94,5 +140,6 @@ examples:
94140
"bus";
95141
#clock-cells = <1>;
96142
#reset-cells = <1>;
143+
#interconnect-cells = <1>;
97144
};
98145
...

‎Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml‎

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@@ -18,6 +18,7 @@ properties:
1818
compatible:
1919
enum:
2020
- qcom,glymur-rpmh-clk
21+
- qcom,kaanapali-rpmh-clk
2122
- qcom,milos-rpmh-clk
2223
- qcom,qcs615-rpmh-clk
2324
- qcom,qdu1000-rpmh-clk

‎Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml‎

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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
77
title: Qualcomm Video Clock & Reset Controller on SM8450
88

99
maintainers:
10-
- Taniya Das <quic_tdas@quicinc.com>
10+
- Taniya Das <taniya.das@oss.qualcomm.com>
1111
- Jagadeesh Kona <quic_jkona@quicinc.com>
1212

1313
description: |
@@ -17,6 +17,7 @@ description: |
1717
See also:
1818
include/dt-bindings/clock/qcom,sm8450-videocc.h
1919
include/dt-bindings/clock/qcom,sm8650-videocc.h
20+
include/dt-bindings/clock/qcom,sm8750-videocc.h
2021
2122
properties:
2223
compatible:
@@ -25,6 +26,7 @@ properties:
2526
- qcom,sm8475-videocc
2627
- qcom,sm8550-videocc
2728
- qcom,sm8650-videocc
29+
- qcom,sm8750-videocc
2830
- qcom,x1e80100-videocc
2931

3032
clocks:
@@ -61,6 +63,7 @@ allOf:
6163
enum:
6264
- qcom,sm8450-videocc
6365
- qcom,sm8550-videocc
66+
- qcom,sm8750-videocc
6467
then:
6568
required:
6669
- required-opps

‎Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml‎

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2525
items:
2626
- enum:
2727
- qcom,glymur-tcsr
28+
- qcom,kaanapali-tcsr
2829
- qcom,milos-tcsr
2930
- qcom,sar2130p-tcsr
3031
- qcom,sm8550-tcsr

‎Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml‎

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@@ -13,11 +13,15 @@ description: |
1313
Qualcomm global clock control module provides the clocks, resets and power
1414
domains on SM8750
1515
16-
See also: include/dt-bindings/clock/qcom,sm8750-gcc.h
16+
See also:
17+
include/dt-bindings/clock/qcom,kaanapali-gcc.h
18+
include/dt-bindings/clock/qcom,sm8750-gcc.h
1719
1820
properties:
1921
compatible:
20-
const: qcom,sm8750-gcc
22+
enum:
23+
- qcom,kaanapali-gcc
24+
- qcom,sm8750-gcc
2125

2226
clocks:
2327
items:

‎Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml‎

Lines changed: 58 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -32,9 +32,36 @@ properties:
3232
- description: PCIe 5 pipe clock
3333
- description: PCIe 6a pipe clock
3434
- description: PCIe 6b pipe clock
35-
- description: USB QMP Phy 0 clock source
36-
- description: USB QMP Phy 1 clock source
37-
- description: USB QMP Phy 2 clock source
35+
- description: USB4_0 QMPPHY clock source
36+
- description: USB4_1 QMPPHY clock source
37+
- description: USB4_2 QMPPHY clock source
38+
- description: USB4_0 PHY DP0 GMUX clock source
39+
- description: USB4_0 PHY DP1 GMUX clock source
40+
- description: USB4_0 PHY PCIE PIPEGMUX clock source
41+
- description: USB4_0 PHY PIPEGMUX clock source
42+
- description: USB4_0 PHY SYS PCIE PIPEGMUX clock source
43+
- description: USB4_1 PHY DP0 GMUX 2 clock source
44+
- description: USB4_1 PHY DP1 GMUX 2 clock source
45+
- description: USB4_1 PHY PCIE PIPEGMUX clock source
46+
- description: USB4_1 PHY PIPEGMUX clock source
47+
- description: USB4_1 PHY SYS PCIE PIPEGMUX clock source
48+
- description: USB4_2 PHY DP0 GMUX 2 clock source
49+
- description: USB4_2 PHY DP1 GMUX 2 clock source
50+
- description: USB4_2 PHY PCIE PIPEGMUX clock source
51+
- description: USB4_2 PHY PIPEGMUX clock source
52+
- description: USB4_2 PHY SYS PCIE PIPEGMUX clock source
53+
- description: USB4_0 PHY RX 0 clock source
54+
- description: USB4_0 PHY RX 1 clock source
55+
- description: USB4_1 PHY RX 0 clock source
56+
- description: USB4_1 PHY RX 1 clock source
57+
- description: USB4_2 PHY RX 0 clock source
58+
- description: USB4_2 PHY RX 1 clock source
59+
- description: USB4_0 PHY PCIE PIPE clock source
60+
- description: USB4_0 PHY max PIPE clock source
61+
- description: USB4_1 PHY PCIE PIPE clock source
62+
- description: USB4_1 PHY max PIPE clock source
63+
- description: USB4_2 PHY PCIE PIPE clock source
64+
- description: USB4_2 PHY max PIPE clock source
3865

3966
power-domains:
4067
description:
@@ -67,7 +94,34 @@ examples:
6794
<&pcie6b_phy>,
6895
<&usb_1_ss0_qmpphy 0>,
6996
<&usb_1_ss1_qmpphy 1>,
70-
<&usb_1_ss2_qmpphy 2>;
97+
<&usb_1_ss2_qmpphy 2>,
98+
<&usb4_0_phy_dp0_gmux_clk>,
99+
<&usb4_0_phy_dp1_gmux_clk>,
100+
<&usb4_0_phy_pcie_pipegmux_clk>,
101+
<&usb4_0_phy_pipegmux_clk>,
102+
<&usb4_0_phy_sys_pcie_pipegmux_clk>,
103+
<&usb4_1_phy_dp0_gmux_2_clk>,
104+
<&usb4_1_phy_dp1_gmux_2_clk>,
105+
<&usb4_1_phy_pcie_pipegmux_clk>,
106+
<&usb4_1_phy_pipegmux_clk>,
107+
<&usb4_1_phy_sys_pcie_pipegmux_clk>,
108+
<&usb4_2_phy_dp0_gmux_2_clk>,
109+
<&usb4_2_phy_dp1_gmux_2_clk>,
110+
<&usb4_2_phy_pcie_pipegmux_clk>,
111+
<&usb4_2_phy_pipegmux_clk>,
112+
<&usb4_2_phy_sys_pcie_pipegmux_clk>,
113+
<&usb4_0_phy_rx_0_clk>,
114+
<&usb4_0_phy_rx_1_clk>,
115+
<&usb4_1_phy_rx_0_clk>,
116+
<&usb4_1_phy_rx_1_clk>,
117+
<&usb4_2_phy_rx_0_clk>,
118+
<&usb4_2_phy_rx_1_clk>,
119+
<&usb4_0_phy_pcie_pipe_clk>,
120+
<&usb4_0_phy_max_pipe_clk>,
121+
<&usb4_1_phy_pcie_pipe_clk>,
122+
<&usb4_1_phy_max_pipe_clk>,
123+
<&usb4_2_phy_pcie_pipe_clk>,
124+
<&usb4_2_phy_max_pipe_clk>;
71125
power-domains = <&rpmhpd RPMHPD_CX>;
72126
#clock-cells = <1>;
73127
#reset-cells = <1>;

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